IBM EM78P259N/260N manual Select Segment

Page 39

EM78P259N/260N

8-Bit Microprocessor with OTP ROM

Case [c] If Comparator output status change is used to wake-up the EM78P259N/ 260N and CMPWE bit of the RE register is enabled before SLEP, WDT must be disabled by software. Hence, the EM78P259N/260N can be awakened only with Case 4. Wake-up time is dependent on the oscillator mode. In RC mode the Wake-up time is 32 clocks (for stable oscillators). In High Crystal mode, Wake-up time is 2ms and 32 clocks (for stable oscillators); and in low Crystal mode, Wake-up time is 500ms.

Case [d] If AD conversion completed is used to wake-up the EM78P259N/260N and ADWE bit of RE register is enabled before SLEP, WDT must be disabled by software. Hence, the EM78P259N/260N can be awakened only with Case 5. The wake-up time is 15 TAD (ADC clock period).

If Port 5 Input Status Change Interrupt is used to wake up the EM78P259N/260N (as in Case [b] above), the following instructions must be executed before SLEP:

BC

R3, 7

; Select Segment 0

MOV

A, @00xx1110b

; Select WDT prescaler and Disable WDT

IOW

IOCE0

; Clear WDT and prescaler

WDTC

R5, R5

MOV

; Read Port 5

ENI (or DISI)

A, @xxxxxx1xb

; Enable (or disable) global interrupt

MOV

; Enable Port 5 input change wake-up bit

MOV

RE

; Enable Port 5 input change interrupt

MOV

A, @xxxxxx1xb

IOW

IOCF0

; Sleep

SLEP

 

Similarly, if the Comparator Interrupt is used to wake up the EM78P259N/260N (as in Case [c] above), the following instructions must be executed before SLEP:

BC

R3, 7

; Select Segment 0

MOV

A, @xxx10XXXb

; Select a comparator and P64 act as CO

IOW

IOC80

pin

; Select WDT prescaler and Disable WDT,

MOV

A, @00x11110b

 

 

and enable comparator output status

IOW

IOCE0

change interrupt

; Clear WDT and prescaler

WDTC

 

ENI (or DISI)

A, @xxx0x1xxb

; Enable (or disable) global interrupt

MOV

; Enable comparator output status

MOV

RE

change wake-up bit

; Sleep

SLEP

 

Product Specification (V1.2) 05.18.2007

• 33

(This specification is subject to change without further notice)

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Contents EM78P259N/260N Elan Microelectronics Corporation Contents 6.1 Reset and Wake-upTCC/WDT and Prescaler Analog-To-Digital Converter ADC11.4 11.111.2 11.3Date Doc. Version Revision DescriptionFeatures General DescriptionBit Microprocessor with OTP ROM Pin DIP/SOP/SSOP Block DiagramPin Assignment Pin DIP/SOPSymbol Pin No Type Function Pin DescriptionEM78P259NP/M EM78P260NP/M/KM 2 R1 Time Clock /Counter Function DescriptionOperational Registers 1 R0 Indirect Address RegisterEM78P259N/260N Cont Bit Microprocessor with OTP ROM Data Memory ConfigurationBits 5~0 5 R4 RAM Select RegisterBit 4 T BitBit 7 ~ Bit Bit 7 ~ Bit 4 C3 ~ C0 Calibrator of internal RC mode6 R5 ~ R6 Port 5 ~ Port 7 R7 Port8 R8 Aisr ADC Input Select Register Bit 3 Adpd 9 R9 Adcon ADC Control RegisterBit 2 ~ Bit 0 Unimplemented, read as ‘0’ RA Adoc ADC Offset Calibration RegisterRB Addata Converted Value of ADC Bit 5 ~ Bit 3 VOF2 ~ VOF0 Offset voltage bitsRC ADDATA1H Converted Value of ADC RD ADDATA1L Converted Value of ADCRE Interrupt Status 2 & Wake-up Control Register RF Interrupt Status 2 Register 16 R10 ~ R3FAll of these are 8-bit general-purpose registers Special Purpose Registers AccumulatorControl Register Bit 4 & Bit 3 COS1 & COS0 Comparator/OP Select bits 3 IOC50 ~ IOC70 I/O Port Control Register4 IOC80 Comparator and Tcca Control Register Bit 7 & Bit 6 Not usedBit 0 Tcccte Tccc signal edge Bit 6 Tccben Tccb enable bit 0 = disable TccbBit 4 Tccbte Tccb signal edge Tccc signal sourceIOCA0 IR and Tccc Scale Control Register Bit 0 Iroute Bit 3 IREBit 2 HF Bit 1 LGPBit OD67 OD66 OD65 OD64 OD63 OD62 OD61 OD60 IOCB0 Pull-down Control RegisterIOCC0 Open-Drain Control Register Bit PD57 PD56 PD55 PD54 PD53 PD52 PD51 PD50IOCD0 Pull-high Control Register IOCE0 WDT Control & Interrupt Mask RegistersBit PH57 PH56 PH55 PH54 PH53 PH52 PH51 PH50 IOCF0 Interrupt Mask Register Lpwtif interrupt enable bit= Disable Lpwtif interrupt = Enable Lpwtif interrupt13 IOC61 Tccb Counter 12 IOC51 Tcca Counter15 IOC81 Tccc Counter 14 IOC71 TCCBH/MSB Counter16 IOC91 Low Time Register IOCA1 High Time RegisterIOCB1 High/Low Time Scale Control Register IOCC1 TCC Prescaler Counter Bit 2 ~ Bit 0 LTS2 ~ LTS0 Low time scale bitsTCC prescaler counter can be read and written to TCC/WDT and Prescaler MUX I/O PortsI/O Port and I/O Control Register Circuit for P60 /INT I/O Port and I/O Control Register Circuit for Port 50 ~ P57 Wake-up Wake-up and Interrupt Reset and Wake-upReset and Wake-up Operation Usage of Port 5 Input Change Wake-up/Interrupt FunctionEM78P259N/260N Select Segment Signal Sleep Mode Normal Mode Comparator Following summarizes the initialized values for registers Address Name Reset Type BitName Reset Type Bit HTR7 HTR6 HTR5 HTR4 HTR3 HTR2 HTR1 HTR0 Aisr Tcif Controller Reset Block DiagramInterrupt T and P Status under Status R3 RegisterEvent EM78P259N/260N Interrupt Vector Interrupt Status Priority RetiBit 7 ~ Bit 3 ADE3 Bit 2 ADE2 Analog-to-Digital Converter ADCADC Control Register AISR/R8, ADCON/R9, ADOC/RA 1.1 R8 Aisr ADC Input Select Register1.2 R9 Adcon AD Control Register P54/TCC/VREF Pin Priority High Medium LowP54 While the CPU is operating = ADC is operatingRA Adoc AD Offset Calibration Register AD Conversion Time ADC Operation during Sleep ModeADC Data Register ADDATA/RB, ADDATA1H/RC, ADDATA1L/RD ADC Sampling TimeProgramming Process/Considerations Programming ProcessFollow these steps to obtain data from the ADC Define Bits in Adcon Sample Demo Programs Define a General RegisterDefine a Control Register ADC Control RegisterAD power on Overview Infrared Remote Control Application/PWM Waveform GenerationFcarrier Function DescriptionIRE Irout Programming the Related Registers IR/PWM Related Status/Data RegistersAddress Name Bit EM78P259N/260N Timer/Counter Under Tcca Counter IOC51Under Tccb Counter IOC61 Under Tccc Counter IOC81 Related Tccx Status/Data Registers ComparatorComparator Output External Reference SignalUsing a Comparator as an Operation Amplifier Wake-up from Sleep ModeComparator Interrupt Conditions OscillatorOscillator Modes Oscillator ModesCrystal Oscillator/Ceramic Resonators Crystal Oscillator TypeFrequency C1pF C2pF 18 Serial Mode Crystal/Resonator Circuit Diagram External RC Oscillator Mode40C ~ +85C 3V~5.5V Total Internal RC Oscillator ModeInternal Drift Rate RC Frequency Temperature Cext Rext Average Fosc 5V, 25C Average Fosc 3V, 25CPower-on Considerations External Power-on Reset CircuitProgrammable WDT Time-out Period EM78P260N Residual Voltage ProtectionVdd EM78P259NWord Bit Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit Code OptionCode Option Register Word Word Word1 Bit12 ~ Bit0Bit 2 ~ 0 PR2 ~ PR0 Protect Bits = Pulses equal to 8/fc s is regarded as signal= Pulses equal to 32/fc s is regarded as signal default Bit Microprocessor with OTP ROM Bit 3 HLPBit 1 & Bit 0 RCM1, RCM0 RC mode selection bits Instruction SetCustomer ID Register Word Following are the EM78P259N/260N instruction set Instruction BinaryMnemonic Operation Status Affected Items Rating Absolute Maximum RatingsDC Electrical Characteristics Symbol Parameter Condition Min Typ Max UnitTa=25 C, VDD=5.0V±5%, VSS=0V Voltage Min Typ Max Internal RC Drift RateVdd=2.5V to 5.5V, Vss=0V, Ta=25C AD Converter CharacteristicsComparator OP Characteristics Device CharacteristicsVdd = 5.0V, Vss=0V, Ta=25C AC Electrical Characteristic Symbol Parameter Conditions Min Typ Max UnitTa=25C, VDD=5V±5%, VSS=0V TCC Input Timing CLKS=0 Timing DiagramsReset Timing CLK=0 AC Test Input/Output WaveformPackage Type Pin Count Package Size Package TypePackage Information 18-Lead Plastic Dual in line Pdip 300 mil838 18-Lead Plastic Small Outline SOP 300 mil650 Lead Plastic Shrink Small Outline Ssop 209 milLead Plastic Dual-in-line Pdip 300 mil Lead Plastic Small Outline SOP 300 mil Quality Assurance and Reliability Address Trap DetectTest Category Test Conditions Remarks
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