IBM EM78P259N/260N IOCC1 TCC Prescaler Counter, Bit 2 ~ Bit 0 LTS2 ~ LTS0 Low time scale bits

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EM78P259N/260N

8-Bit Microprocessor with OTP ROM

Bit 6 ~ Bit 4 (HTS2 ~ HTS0): High time scale bits:

HTS2		HTS1		HTS0		High time Rate

0		0		0		1:2
0		0		1		1:4
0		1		0		1:8
0		1		1		1:16
1		0		0		1:32
1		0		1		1:64
1		1		0		1:128
1		1		1		1:256

Bit 3 (LTSE): Low time scale enable bit.

0 = scale disable bit, Low time rate is 1:1

1 = scale enable bit, Low time rate is set as Bit 2~Bit 0.

Bit 2 ~ Bit 0 (LTS2 ~ LTS0): Low time scale bits:

LTS2		LTS1		LTS0		Low time Rate

0		0		0		1:2
0		0		1		1:4
0		1		0		1:8
0		1		1		1:16
1		0		0		1:32
1		0		1		1:64
1		1		0		1:128
1		1		1		1:256

6.2.19 IOCC1 (TCC Prescaler Counter)

The TCC prescaler counter can be read and written to.

PST2 PST1 PST0 Bit 7 Bit 6 Bit 5 Bit 4

Bit 3		Bit 2		Bit 1		Bit 0	TCC
Bit 3		Bit 2		Bit 1		Bit 0	Rate
							Rate

0	0	0	-	-	-	-	-	-	-	V	1:2
0	0	1	-	-	-	-	-	-	V	V	1:4
0	1	0	-	-	-	-	-	V	V	V	1:8
0	1	1	-	-	-	-	V	V	V	V	1:16
1	0	0	-	-	-	V	V	V	V	V	1:32
1	0	1	-	-	V	V	V	V	V	V	1:64
1	1	0	-	V	V	V	V	V	V	V	1:128
1	1	1	V	V	V	V	V	V	V	V	1:256
										V = valid value

The TCC prescaler counter is assigned to TCC (R1).

The contents of the IOCC1 register are cleared when one of the following occurs:

a value is written to TCC register

a value is written to TCC prescaler bits (Bits 3, 2, 1, 0 of CONT)

power-on reset, /RESET

WDT time-out reset

26 •	Product Specification (V1.2) 05.18.2007
	(This specification is subject to change without further notice)

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Contents EM78P259N/260N Elan Microelectronics Corporation Contents Reset and Wake-up TCC/WDT and PrescalerAnalog-To-Digital Converter ADC 6.111.1 11.211.3 11.4Doc. Version Revision Description DateBit Microprocessor with OTP ROM FeaturesGeneral Description Block Diagram Pin AssignmentPin DIP/SOP Pin DIP/SOP/SSOPEM78P259NP/M Symbol Pin No Type FunctionPin Description EM78P260NP/M/KM Function Description Operational Registers1 R0 Indirect Address Register 2 R1 Time Clock /CounterEM78P259N/260N Bit Microprocessor with OTP ROM Data Memory Configuration Cont5 R4 RAM Select Register Bit 4 TBit Bits 5~0Bit 7 ~ Bit 4 C3 ~ C0 Calibrator of internal RC mode 6 R5 ~ R6 Port 5 ~ Port7 R7 Port Bit 7 ~ Bit8 R8 Aisr ADC Input Select Register 9 R9 Adcon ADC Control Register Bit 3 AdpdRA Adoc ADC Offset Calibration Register RB Addata Converted Value of ADCBit 5 ~ Bit 3 VOF2 ~ VOF0 Offset voltage bits Bit 2 ~ Bit 0 Unimplemented, read as ‘0’RE Interrupt Status 2 & Wake-up Control Register RC ADDATA1H Converted Value of ADCRD ADDATA1L Converted Value of ADC All of these are 8-bit general-purpose registers RF Interrupt Status 2 Register16 R10 ~ R3F Control Register Special Purpose RegistersAccumulator 3 IOC50 ~ IOC70 I/O Port Control Register 4 IOC80 Comparator and Tcca Control RegisterBit 7 & Bit 6 Not used Bit 4 & Bit 3 COS1 & COS0 Comparator/OP Select bitsBit 6 Tccben Tccb enable bit 0 = disable Tccb Bit 4 Tccbte Tccb signal edgeTccc signal source Bit 0 Tcccte Tccc signal edgeIOCA0 IR and Tccc Scale Control Register Bit 3 IRE Bit 2 HFBit 1 LGP Bit 0 IrouteIOCB0 Pull-down Control Register IOCC0 Open-Drain Control RegisterBit PD57 PD56 PD55 PD54 PD53 PD52 PD51 PD50 Bit OD67 OD66 OD65 OD64 OD63 OD62 OD61 OD60Bit PH57 PH56 PH55 PH54 PH53 PH52 PH51 PH50 IOCD0 Pull-high Control RegisterIOCE0 WDT Control & Interrupt Mask Registers Lpwtif interrupt enable bit = Disable Lpwtif interrupt= Enable Lpwtif interrupt IOCF0 Interrupt Mask Register12 IOC51 Tcca Counter 13 IOC61 Tccb Counter14 IOC71 TCCBH/MSB Counter 15 IOC81 Tccc CounterIOCB1 High/Low Time Scale Control Register 16 IOC91 Low Time RegisterIOCA1 High Time Register TCC prescaler counter can be read and written to IOCC1 TCC Prescaler CounterBit 2 ~ Bit 0 LTS2 ~ LTS0 Low time scale bits TCC/WDT and Prescaler I/O Ports MUXI/O Port and I/O Control Register Circuit for P60 /INT I/O Port and I/O Control Register Circuit for Port 50 ~ P57 Reset and Wake-up Reset and Wake-up OperationUsage of Port 5 Input Change Wake-up/Interrupt Function Wake-up Wake-up and InterruptEM78P259N/260N Select Segment Signal Sleep Mode Normal Mode Comparator Address Name Reset Type Bit Following summarizes the initialized values for registersName Reset Type Bit HTR7 HTR6 HTR5 HTR4 HTR3 HTR2 HTR1 HTR0 Aisr Controller Reset Block Diagram TcifEvent InterruptT and P Status under Status R3 Register EM78P259N/260N Reti Interrupt Vector Interrupt Status PriorityAnalog-to-Digital Converter ADC ADC Control Register AISR/R8, ADCON/R9, ADOC/RA1.1 R8 Aisr ADC Input Select Register Bit 7 ~ Bit 3 ADE3 Bit 2 ADE2P54 1.2 R9 Adcon AD Control RegisterP54/TCC/VREF Pin Priority High Medium Low RA Adoc AD Offset Calibration Register While the CPU is operating= ADC is operating ADC Operation during Sleep Mode ADC Data Register ADDATA/RB, ADDATA1H/RC, ADDATA1L/RDADC Sampling Time AD Conversion TimeFollow these steps to obtain data from the ADC Programming Process/ConsiderationsProgramming Process Sample Demo Programs Define a General Register Define a Control RegisterADC Control Register Define Bits in AdconAD power on Infrared Remote Control Application/PWM Waveform Generation OverviewFunction Description FcarrierIRE Irout Address Name Bit Programming the Related RegistersIR/PWM Related Status/Data Registers EM78P259N/260N Under Tccb Counter IOC61 Timer/CounterUnder Tcca Counter IOC51 Under Tccc Counter IOC81 Comparator Related Tccx Status/Data RegistersExternal Reference Signal Comparator OutputComparator Interrupt Using a Comparator as an Operation AmplifierWake-up from Sleep Mode Oscillator Oscillator ModesOscillator Modes ConditionsFrequency C1pF C2pF Crystal Oscillator/Ceramic Resonators CrystalOscillator Type External RC Oscillator Mode 18 Serial Mode Crystal/Resonator Circuit DiagramInternal RC Oscillator Mode Internal Drift Rate RC Frequency TemperatureCext Rext Average Fosc 5V, 25C Average Fosc 3V, 25C 40C ~ +85C 3V~5.5V TotalProgrammable WDT Time-out Period Power-on ConsiderationsExternal Power-on Reset Circuit Residual Voltage Protection VddEM78P259N EM78P260NCode Option Code Option Register WordWord Word1 Bit12 ~ Bit0 Word Bit Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit= Pulses equal to 8/fc s is regarded as signal = Pulses equal to 32/fc s is regarded as signal defaultBit Microprocessor with OTP ROM Bit 3 HLP Bit 2 ~ 0 PR2 ~ PR0 Protect BitsCustomer ID Register Word Bit 1 & Bit 0 RCM1, RCM0 RC mode selection bitsInstruction Set Mnemonic Operation Status Affected Following are the EM78P259N/260N instruction setInstruction Binary Absolute Maximum Ratings Items RatingTa=25 C, VDD=5.0V±5%, VSS=0V DC Electrical CharacteristicsSymbol Parameter Condition Min Typ Max Unit Internal RC Drift Rate Voltage Min Typ MaxAD Converter Characteristics Vdd=2.5V to 5.5V, Vss=0V, Ta=25CVdd = 5.0V, Vss=0V, Ta=25C Comparator OP CharacteristicsDevice Characteristics Ta=25C, VDD=5V±5%, VSS=0V AC Electrical CharacteristicSymbol Parameter Conditions Min Typ Max Unit Timing Diagrams Reset Timing CLK=0AC Test Input/Output Waveform TCC Input Timing CLKS=0Package Type Package Information18-Lead Plastic Dual in line Pdip 300 mil Package Type Pin Count Package Size18-Lead Plastic Small Outline SOP 300 mil 838Lead Plastic Shrink Small Outline Ssop 209 mil 650Lead Plastic Dual-in-line Pdip 300 mil Lead Plastic Small Outline SOP 300 mil Test Category Test Conditions Remarks Quality Assurance and ReliabilityAddress Trap Detect