IBM EM78P259N/260N manual ADC Data Register ADDATA/RB, ADDATA1H/RC, ADDATA1L/RD, ADC Sampling Time

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EM78P259N/260N

8-Bit Microprocessor with OTP ROM

6.7.2ADC Data Register (ADDATA/RB, ADDATA1H/RC, ADDATA1L/RD)

When the AD conversion is completed, the result is loaded to the ADDATA, ADDATA1H and ADDATA1L registers. The ADRUN bit is cleared, and the ADIF is set.

6.7.3 ADC Sampling Time

The accuracy, linearity, and speed of the successive approximation of AD converter are dependent on the properties of the ADC and the comparator. The source impedance and the internal sampling impedance directly affect the time required to charge the sample holding capacitor. The application program controls the length of the sample time to meet the specified accuracy. Generally speaking, the program should wait for 2μs for each KΩ of the analog source impedance and at least 2μs for the low-impedance source. The maximum recommended impedance for analog source is 10KΩ at Vdd=5V. After the analog input channel is selected, this acquisition time must be done before the conversion is started.

6.7.4 AD Conversion Time

CKR1 and CKR0 select the conversion time (Tct), in terms of instruction cycles. This allows the MCU to run at a maximum frequency without sacrificing the AD conversion accuracy. For the EM78P259N/260N, the conversion time per bit is about 4μs. The table below shows the relationship between Tct and the maximum operating frequencies.

CKR1:CKR0

 

Operation

Max. Operation

Max. Conversion

 

Mode

Frequency

Rate/Bit

 

 

Max. Conversion Rate

00

Fosc/16

4 MHz

250kHz (4μs)

15*4μs=60μs (16.7kHz)

01

Fosc/4

1 MHz

250kHz (4μs)

15*4μs=60μs (16.7kHz)

10

Fosc/64

16 MHz

250kHz ( 4μs)

15*4μs=60μs (16.7kHz)

11

Internal RC

–

14kHz (71μs)

15*71μs=1065μs (0.938kHz)

NOTE

■Pin not used as an analog input pin can be used as a regular input or output pin.

■During conversion, do not perform output instruction to maintain precision for all of the pins.

6.7.5 ADC Operation during Sleep Mode

In order to obtain a more accurate ADC value and reduce power consumption, the AD conversion remains operational during sleep mode. As the SLEP instruction is executed, all the MCU operations will stop except for the Oscillators TCC, TCCA, TCCB, TCCC and AD conversion.

The AD Conversion is considered completed as determined by:

1.ADRUN bit of R9 register is cleared (“0” value).

2.ADIF bit of RE register is set to “1”.

Product Specification (V1.2) 05.18.2007

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(This specification is subject to change without further notice)

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Contents EM78P259N/260N Elan Microelectronics Corporation Contents TCC/WDT and Prescaler Reset and Wake-upAnalog-To-Digital Converter ADC 6.111.2 11.111.3 11.4Date Doc. Version Revision DescriptionBit Microprocessor with OTP ROM FeaturesGeneral Description Pin Assignment Block DiagramPin DIP/SOP Pin DIP/SOP/SSOPEM78P259NP/M Symbol Pin No Type FunctionPin Description EM78P260NP/M/KM Operational Registers Function Description1 R0 Indirect Address Register 2 R1 Time Clock /CounterEM78P259N/260N Cont Bit Microprocessor with OTP ROM Data Memory ConfigurationBit 4 T 5 R4 RAM Select RegisterBit Bits 5~06 R5 ~ R6 Port 5 ~ Port Bit 7 ~ Bit 4 C3 ~ C0 Calibrator of internal RC mode7 R7 Port Bit 7 ~ Bit8 R8 Aisr ADC Input Select Register Bit 3 Adpd 9 R9 Adcon ADC Control RegisterRB Addata Converted Value of ADC RA Adoc ADC Offset Calibration RegisterBit 5 ~ Bit 3 VOF2 ~ VOF0 Offset voltage bits Bit 2 ~ Bit 0 Unimplemented, read as ‘0’RE Interrupt Status 2 & Wake-up Control Register RC ADDATA1H Converted Value of ADCRD ADDATA1L Converted Value of ADC All of these are 8-bit general-purpose registers RF Interrupt Status 2 Register16 R10 ~ R3F Control Register Special Purpose RegistersAccumulator 4 IOC80 Comparator and Tcca Control Register 3 IOC50 ~ IOC70 I/O Port Control RegisterBit 7 & Bit 6 Not used Bit 4 & Bit 3 COS1 & COS0 Comparator/OP Select bitsBit 4 Tccbte Tccb signal edge Bit 6 Tccben Tccb enable bit 0 = disable TccbTccc signal source Bit 0 Tcccte Tccc signal edgeIOCA0 IR and Tccc Scale Control Register Bit 2 HF Bit 3 IREBit 1 LGP Bit 0 IrouteIOCC0 Open-Drain Control Register IOCB0 Pull-down Control RegisterBit PD57 PD56 PD55 PD54 PD53 PD52 PD51 PD50 Bit OD67 OD66 OD65 OD64 OD63 OD62 OD61 OD60Bit PH57 PH56 PH55 PH54 PH53 PH52 PH51 PH50 IOCD0 Pull-high Control RegisterIOCE0 WDT Control & Interrupt Mask Registers = Disable Lpwtif interrupt Lpwtif interrupt enable bit= Enable Lpwtif interrupt IOCF0 Interrupt Mask Register13 IOC61 Tccb Counter 12 IOC51 Tcca Counter15 IOC81 Tccc Counter 14 IOC71 TCCBH/MSB CounterIOCB1 High/Low Time Scale Control Register 16 IOC91 Low Time RegisterIOCA1 High Time Register TCC prescaler counter can be read and written to IOCC1 TCC Prescaler CounterBit 2 ~ Bit 0 LTS2 ~ LTS0 Low time scale bits TCC/WDT and Prescaler MUX I/O PortsI/O Port and I/O Control Register Circuit for P60 /INT I/O Port and I/O Control Register Circuit for Port 50 ~ P57 Reset and Wake-up Operation Reset and Wake-upUsage of Port 5 Input Change Wake-up/Interrupt Function Wake-up Wake-up and InterruptEM78P259N/260N Select Segment Signal Sleep Mode Normal Mode Comparator Following summarizes the initialized values for registers Address Name Reset Type BitName Reset Type Bit HTR7 HTR6 HTR5 HTR4 HTR3 HTR2 HTR1 HTR0 Aisr Tcif Controller Reset Block DiagramEvent InterruptT and P Status under Status R3 Register EM78P259N/260N Interrupt Vector Interrupt Status Priority RetiADC Control Register AISR/R8, ADCON/R9, ADOC/RA Analog-to-Digital Converter ADC1.1 R8 Aisr ADC Input Select Register Bit 7 ~ Bit 3 ADE3 Bit 2 ADE2P54 1.2 R9 Adcon AD Control RegisterP54/TCC/VREF Pin Priority High Medium Low RA Adoc AD Offset Calibration Register While the CPU is operating= ADC is operating ADC Data Register ADDATA/RB, ADDATA1H/RC, ADDATA1L/RD ADC Operation during Sleep ModeADC Sampling Time AD Conversion TimeFollow these steps to obtain data from the ADC Programming Process/ConsiderationsProgramming Process Define a Control Register Sample Demo Programs Define a General RegisterADC Control Register Define Bits in AdconAD power on Overview Infrared Remote Control Application/PWM Waveform GenerationFcarrier Function DescriptionIRE Irout Address Name Bit Programming the Related RegistersIR/PWM Related Status/Data Registers EM78P259N/260N Under Tccb Counter IOC61 Timer/CounterUnder Tcca Counter IOC51 Under Tccc Counter IOC81 Related Tccx Status/Data Registers ComparatorComparator Output External Reference SignalComparator Interrupt Using a Comparator as an Operation AmplifierWake-up from Sleep Mode Oscillator Modes OscillatorOscillator Modes ConditionsFrequency C1pF C2pF Crystal Oscillator/Ceramic Resonators CrystalOscillator Type 18 Serial Mode Crystal/Resonator Circuit Diagram External RC Oscillator ModeInternal Drift Rate RC Frequency Temperature Internal RC Oscillator ModeCext Rext Average Fosc 5V, 25C Average Fosc 3V, 25C 40C ~ +85C 3V~5.5V TotalProgrammable WDT Time-out Period Power-on ConsiderationsExternal Power-on Reset Circuit Vdd Residual Voltage ProtectionEM78P259N EM78P260NCode Option Register Word Code OptionWord Word1 Bit12 ~ Bit0 Word Bit Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit= Pulses equal to 32/fc s is regarded as signal default = Pulses equal to 8/fc s is regarded as signalBit Microprocessor with OTP ROM Bit 3 HLP Bit 2 ~ 0 PR2 ~ PR0 Protect BitsCustomer ID Register Word Bit 1 & Bit 0 RCM1, RCM0 RC mode selection bitsInstruction Set Mnemonic Operation Status Affected Following are the EM78P259N/260N instruction setInstruction Binary Items Rating Absolute Maximum RatingsTa=25 C, VDD=5.0V±5%, VSS=0V DC Electrical CharacteristicsSymbol Parameter Condition Min Typ Max Unit Voltage Min Typ Max Internal RC Drift RateVdd=2.5V to 5.5V, Vss=0V, Ta=25C AD Converter CharacteristicsVdd = 5.0V, Vss=0V, Ta=25C Comparator OP CharacteristicsDevice Characteristics Ta=25C, VDD=5V±5%, VSS=0V AC Electrical CharacteristicSymbol Parameter Conditions Min Typ Max Unit Reset Timing CLK=0 Timing DiagramsAC Test Input/Output Waveform TCC Input Timing CLKS=0Package Information Package Type18-Lead Plastic Dual in line Pdip 300 mil Package Type Pin Count Package Size838 18-Lead Plastic Small Outline SOP 300 mil650 Lead Plastic Shrink Small Outline Ssop 209 milLead Plastic Dual-in-line Pdip 300 mil Lead Plastic Small Outline SOP 300 mil Test Category Test Conditions Remarks Quality Assurance and ReliabilityAddress Trap Detect
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