Inova ICP-PII user manual Specifications, Mobile Piii

Product Overview ICP-PIII

1.1 Specifications

Processor	Socket 370 BGA (mobile) or FC-PGA based Intel Pentium III or Celeron
Pentium III	Up to 1000MHz
	(100MHz PSB, 256kByte L2 cache)
Mobile PIII	Up to 700MHz BGA2 package with interposer
	(100MHz PSB, 256kByte L2 cache)

Mobile Celeron BGA2 package with interposer (100Mz PSB, 128kByte L2 cache)

L2 Cache	128/256kByte L2 cache depending on processor
Memory	128MByte soldered synchronous DRAM with optional BIOS activated
	ECC feature. Additional Piggyback provides additional 128MByte,
	or 384MByte
FLASH-Disk	Available as an option (Disk-on-Chip™) providing up to 500MByte FLASH
Battery	Lithium cell for RTC (NV-RAM) with a lifetime > 8 years
North Bridge	440BX North Bridge 82443BX supporting:
	A 100MHz system bus DRAM controller with 64bit, 100MHz
	A	SDRAM interface
		ECC support
	A	AGP 2X interface (66/133MHz)
	A	Power management
South Bridge	M1543C:
	A	PCI/ISA Bridge
	A	Super I/O: 1 Floppy Disk Controller, 1 Parallel Port, 2 Serial Ports
	A	Fast IR
	A IDE Controller (4 devices)
	A	Ultra 66 DMA support
	A	12Mbit/s USB controller
	A	Interrupt controller
	A	Power Management Unit
	A	Full support for ACPI and OS directed power management
	A Mouse & keyboard controller
Graphics	Lynx3DM or Radeon VE graphic accelerator
	A	8/16Mbyte SGRAM/SDRAM
	A	3D graphics, DVD & MPEG-2 support
	A	Multi-Display
	A Dual View support under Microsoft Windows® 9x, Windows® NT®
	A	& Windows® 2000
		CRT / TFT resolutions up to 2048x1536
	A GigaST)R / PanelLink™ or TFT Piggyback
		Dual display option or TFT will require dedicated front-panel.
Recovery BIOS	FLASH Recovery BIOS
Watchdog	Programmable up to 10 minutes; issues NMI or Reset

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