Inova user manual PrefaceICP-PIII

PrefaceICP-PIII

1.4	Hardware		1-10
1.41 Block Diagram			1-10
Figure 1.41 Block Diagram			1-10
1.42 Connector Location			1-11
Figure 1.42 Connector Locations			1-11
1.43 Connector Description			1-11
Table 1.43 Connector Description			1-11
Table 1.43 Continued			1-12
1.44 Front-Panel Features			1-12
Table 1.44 Front Panels			1-12
Figure 1.44 Front-Panel Options			1-13
1.45 Interface Positions			1-14
Figure 1.45 Interfaces			1-14
2.0	Memory Map		2-2
Figure 2.00 System Architecture			2-2
Table 2.00 UMB Reservations for ISA			2-3
Table 2.01 Port Addressing			2-3
2.1	I/O Mapped Peripherals		2-4
Table 2.10 Legacy I/O Map (ISA Compatible)			2-4
2.2	Memory Mapped Peripherals ..... 2-5
2.3	Interrupt Routing		2-5
Table 2.30 PC-AT Interrupt Definitions			2-6
2.4	Inova PIII Device List		2-7
Table 2.40 Legacy I/O Map (ISA Compatible)			2-7
2.5	Interrupt Configuration		2-8
Table 2.50 CompactPCI Bus Interrupts			2-8
2.6	Timer / Counter		2-9
2.7	Watchdog		2-9
3.0	CompactPCI J1/J2 Connector...		3-3
3.01 CompactPCI Connector			3-3
Figure 3.01 The 32-Bit CompactPCI Bus Interface Connector			3-3
3.02 ICP-PIII Connector J1 and J2			3-3
Table 3.02 Inova’s ICP-PIII32-Bit CompactPCI J1 Pin Assignment			3-4
Table 3.03		Inova’s ICP-PIII32-Bit CompactPCI J2 Pin Assignment (Standard)	3-5
Table 3.04		Inova’s ICP-PIII32-Bit CompactPCI J2 Pin Assignment for Rear I/O (A)	3-6
Table 3.05		Inova’s ICP-PIII32-Bit CompactPCI J2 Pin Assignment for Rear I/O (B)	3-7
Table 3.06		Inova’s ICP-PIII32-Bit CompactPCI J2 Pin Assignment for Rear I/O (C)	3-8
Table 3.07		Inova’s ICP-PIII Rear I/O J2 (CPU) Integration	3-9

Page 0-2 ©2002 Inova Computers GmbH Doc. PD00581013.004