Texas Instruments TMS320x28xx, 28xxx Phase Locking the Time-Base Clocks of Multiple ePWM Modules

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Time-Base (TB) Submodule

2.2.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules

The TBCLKSYNC bit can be used to globally synchronize the time-base clocks of all enabled ePWM modules on a device. This bit is part of the DSPs clock enable registers and is described in the specific device version of the System Control and Interrupts Reference Guide listed in Section 1. When TBCLKSYNC = 0, the time-base clock of all ePWM modules is stopped (default). When TBCLKSYNC = 1, all ePWM time-base clocks are started with the rising edge of TBCLK aligned. For perfectly synchronized TBCLKs, the prescaler bits in the TBCTL register of each ePWM module must be set identically. The proper procedure for enabling the ePWM clocks is as follows:

1.Enable the individual ePWM module clocks. This is described in the specific device version of the System Control and Interrupts Reference Guide listed in Section 1.

2.Set TBCLKSYNC = 0. This will stop the time-base clock within any enabled ePWM module.

3.Configure the prescaler values and desired ePWM modes.

4.Set TBCLKSYNC = 1.

2.2.5Time-base Counter Modes and Timing Waveforms

The time-base counter operates in one of four modes:

∙Up-count mode which is asymmetrical.

∙Down-count mode which is asymmetrical.

∙Up-down-count which is symmetrical

∙Frozen where the time-base counter is held constant at the current value

To illustrate the operation of the first three modes, the following timing diagrams show when events are generated and how the time-base responds to an EPWMxSYNCI signal.

Figure 2-7. Time-Base Up-Count Mode Waveforms

	TBCTR[15:0]
	0xFFFF
	TBPRD
	(value)
	TBPHS
	(value)
	0000
	EPWMxSYNCI
	CTR_dir
	CTR = zero
	CTR = PRD
	CNT_max
30	ePWM Submodules	SPRU791D–November 2004–Revised October 2007

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