Texas Instruments 28xxx manual Event-Trigger Prescale Register Etps Field Descriptions, Socb Soca

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		Event-Trigger Submodule Registers
	Table 4-24. Event-Trigger Prescale Register (ETPS) Field Descriptions (continued)
Bits	Name	Description
9-8	SOCAPRD	ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Period Select
		These bits determine how many selected ETSEL[SOCASEL] events need to occur before an
		EPWMxSOCA pulse is generated. To be generated, the pulse must be enabled
		(ETSEL[SOCAEN] = 1). The SOCA pulse will be generated even if the status flag is set from
		a previous start of conversion (ETFLG[SOCA] = 1). Once the SOCA pulse is generated, the
		ETPS[SOCACNT] bits will automatically be cleared.
	00	Disable the SOCA event counter. No EPWMxSOCA pulse will be generated
	01	Generate the EPWMxSOCA pulse on the first event: ETPS[SOCACNT] = 0,1
	10	Generate the EPWMxSOCA pulse on the second event: ETPS[SOCACNT] = 1,0
	11	Generate the EPWMxSOCA pulse on the third event: ETPS[SOCACNT] = 1,1
7-4	Reserved	Reserved
3-2	INTCNT	ePWM Interrupt Event (EPWMx_INT) Counter Register
		These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are
		automatically cleared when an interrupt pulse is generated. If interrupts are disabled,
		ETSEL[INT] = 0 or the interrupt flag is set, ETFLG[INT] = 1, the counter will stop counting
		events when it reaches the period value ETPS[INTCNT] = ETPS[INTPRD].
	00	No events have occurred.
	01	1 event has occurred.
	10	2 events have occurred.
	11	3 events have occurred.
1-0	INTPRD	ePWM Interrupt (EPWMx_INT) Period Select
		These bits determine how many selected ETSEL[INTSEL] events need to occur before an
		interrupt is generated. To be generated, the interrupt must be enabled (ETSEL[INT] = 1). If
		the interrupt status flag is set from a previous interrupt (ETFLG[INT] = 1) then no interrupt will
		be generated until the flag is cleared via the ETCLR[INT] bit. This allows for one interrupt to
		be pending while another is still being serviced. Once the interrupt is generated, the
		ETPS[INTCNT] bits will automatically be cleared.
		Writing a INTPRD value that is the same as the current counter value will trigger an interrupt
		if it is enabled and the status flag is clear.
		Writing a INTPRD value that is less than the current counter value will result in an undefined
		state.
		If a counter event occurs at the same instant as a new zero or non-zero INTPRD value is
		written, the counter is incremented.
	00	Disable the interrupt event counter. No interrupt will be generated and ETFRC[INT] is
		ignored.
	01	Generate an interrupt on the first event INTCNT = 01 (first event)
	10	Generate interrupt on ETPS[INTCNT] = 1,0 (second event)
	11	Generate interrupt on ETPS[INTCNT] = 1,1 (third event)

Figure 4-25. Event-Trigger Flag Register (ETFLG)

15					8
		Reserved
		R-0
7	4	3	2	1	0
Reserved		SOCB	SOCA	Reserved	INT
R-0		R-0	R-0	R-0	R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

SPRU791D–November 2004–Revised October 2007	Registers	113
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