Texas Instruments TMS320x28xx, 28xxx Action-Qualifier Submodule Possible Input Events, ∙ Set High

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Action-Qualifier (AQ) Submodule

The action-qualifier submodule is based on event-driven logic. It can be thought of as a programmable cross switch with events at the input and actions at the output, all of which are software controlled via the set of registers shown in Table 2-6.

Figure 2-18. Action-Qualifier Submodule Inputs and Outputs

TBCLK

CTR￿=￿PRD

CTR￿=￿Zero

CTR￿=￿CMPA

CTR￿=￿CMPB

CTR_dir

Action-qualifier￿(AQ)￿Module

AQCTLA[15:0]

Action-qualifier￿control￿A

AQCTLB[15:0]

Action-qualifier￿control￿B

AQSFRC[15:0]

Action-qualifier￿S/W￿force

AQCSFRC[3:0]￿(shadow)

continuous￿S/W￿force

AQCSFRC[3:0]￿(active)

continuous￿S/W￿force

EPWMA

EPWMB

For convenience, the possible input events are summarized again in Table 2-7.

Table 2-7. Action-Qualifier Submodule Possible Input Events

Signal

Description

Registers Compared

CTR = PRD

Time-base counter equal to the period value

TBCTR = TBPRD

CTR = Zero

Time-base counter equal to zero

TBCTR = 0x0000

CTR = CMPA

Time-base counter equal to the counter-compare A

TBCTR = CMPA

CTR = CMPB

Time-base counter equal to the counter-compare B

TBCTR = CMPB

Software forced event

Asynchronous event initiated by software

 

The software forced action is a useful asynchronous event. This control is handled by registers AQSFRC and AQCSFRC.

The action-qualifier submodule controls how the two outputs EPWMxA and EPWMxB behave when a particular event occurs. The event inputs to the action-qualifier submodule are further qualified by the counter direction (up or down). This allows for independent action on outputs on both the count-up and count-down phases.

The possible actions imposed on outputs EPWMxA and EPWMxB are:

∙Set High:

Set output EPWMxA or EPWMxB to a high level.

∙Clear Low:

Set output EPWMxA or EPWMxB to a low level.

∙Toggle:

If EPWMxA or EPWMxB is currently pulled high, then pull the output low. If EPWMxA or EPWMxB is currently pulled low, then pull the output high.

∙Do Nothing:

Keep outputs EPWMxA and EPWMxB at same level as currently set. Although the "Do Nothing" option prevents an event from causing an action on the EPWMxA and EPWMxB outputs, this event can still trigger interrupts and ADC start of conversion. See the Event-trigger Submodule description in Section 2.8 for details.

38

ePWM Submodules

SPRU791D–November 2004–Revised October 2007

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Contents Reference Guide Submit Documentation Feedback Contents Controlling a 3-Phase Interleaved DC/DC Converter List of Figures Event-Trigger Socb Pulse Generator Simplified ePWM Module List of Tables Submit Documentation Feedback CPU Users Guides Related Documentation From Texas InstrumentsData Manuals Peripheral GuidesTools Guides Application ReportsTrademarks TMS320C28x, C28x are trademarks of Texas InstrumentsSubmit Documentation Feedback Introduction Introduction Submodule OverviewMultiple ePWM Modules ∙ ADC start-of-conversion signals EPWMxSOCA and EPWMxSOCB ∙ PWM output signals EPWMxA and EPWMxB∙ Trip-zone signals TZ1 to TZ6 ∙ Peripheral BusEPWM Submodules and Critical Internal Signal Interconnects Register MappingTime-Base Submodule Registers Offset Size NameDescription Counter-Compare Submodule RegistersEPWM Submodules Overview Submodule Configuration ParametersSubmodule Configuration Parameter or Option Example 2-1. Constant Definitions Used in the Code Examples TbupChpenable Time-Base TB Submodule Purpose of the Time-Base SubmoduleRegister Controlling and Monitoring the Time-base SubmoduleTime-Base Submodule Registers ∙ Up-Count Mode Key Time-Base Signals∙ Up-Down-Count Mode ∙ Down-Count ModeTime-Base Period Shadow Register ∙ Time-Base Period Shadow Mode∙ Time-Base Period Immediate Load Mode ∙ Active RegisterTime-Base Counter Synchronization Time-Base Counter Synchronization SchemeEPWM11SYNCI EPWM11SYNCO∙ EPWMxSYNCI Synchronization Input Pulse ∙ Software Forced Synchronization PulsePhase Locking the Time-Base Clocks of Multiple ePWM Modules Time-base Counter Modes and Timing WaveformsTime-Base Down-Count Mode Waveforms Counter-Compare CC Submodule 11. Counter-Compare SubmoduleCounter-Compare Submodule Registers Purpose of the Counter-Compare SubmoduleControlling and Monitoring the Counter-Compare Submodule Register Name Address Offset∙ Shadow Mode Count Mode Timing WaveformsCounter-Compare Submodule Key Signals ∙ Immediate Load ModeCTR=CMPA CTR=CMPBCTR = Cmpb Action-Qualifier Submodule Registers Action-Qualifier AQ SubmodulePurpose of the Action-Qualifier Submodule ∙ Clear Low Action-Qualifier Submodule Possible Input Events∙ Set High ∙ ToggleTB Counter equals Actions 10. Action-Qualifier Event Priority for Down-Count Mode Action-Qualifier Event Priority for Up-Down-Count ModeAction-Qualifier Event Priority for Up-Count Mode Action-Qualifier Event PriorityUse up-down-count mode to generate an asymmetric PWM Waveforms for Common ConfigurationsUse up-down-count mode to generate a symmetric PWM When using up-count mode to generate an asymmetric PWM20. Up-Down-Count Mode Symmetrical Waveform Example 2-2. Code Sample for Figure TbctrValue EPWMxA EPWMxB Example 2-3. Code Sample for Figure Tbclk = SysclkoutExample 2-4. Code Sample for Figure EdgePosAExample 2-5. Code Sample for Figure Example 2-6. Code Sample for Figure TbctrExample 2-7. Code Sample for Figure EPWMxA EPWMxBControlling and Monitoring the Dead-Band Submodule Dead-Band Generator DB SubmodulePurpose of the Dead-Band Submodule 12. Dead-Band Generator Submodule Registers∙ Input Source Selection ∙ Output Mode ControlOperational Highlights for the Dead-Band Submodule ∙ Polarity ControlMode Description 13. Classical Dead-Band Operating Modes29. Dead-Band Waveforms for Typical Cases 0% Duty 100% Dead-Band Delay in μS FED = Dbfed × Ttbclk RED = Dbred × TtbclkControlling the PWM-Chopper Submodule PWM-Chopper PC SubmodulePurpose of the PWM-Chopper Submodule Operational Highlights for the PWM-Chopper SubmoduleWaveforms 31. PWM-Chopper Submodule Operational DetailsOSHTWTHz One-Shot Pulse16. Possible Pulse Width Values for Sysclkout = 100 MHz Duty Cycle Control PeriodTrip-Zone TZ Submodule Purpose of the Trip-Zone Submodule17. Trip-Zone Submodule Registers Controlling and Monitoring the Trip-Zone SubmoduleOperational Highlights for the Trip-Zone Submodule ∙ Cycle-by-Cycle CBCScenario a Example 2-8. Trip-Zone Configurations18. Possible Actions On a Trip Event Scenario B36. Trip-Zone Submodule Mode Control Logic Generating Trip Event InterruptsEvent-Trigger ET Submodule 37. Trip-Zone Submodule Interrupt LogicOperational Overview of the Event-Trigger Submodule 19. Event-Trigger Submodule Registers CTR=CMPB CTRD=CMPB41. Event-Trigger Interrupt Generator 42. Event-Trigger Soca Pulse Generator Submit Documentation Feedback Applications to Power Topologies Controlling Multiple Buck Converters With IndependentKey Configuration Capabilities Overview of Multiple ModulesCTR=0 EPWM1B CTR=CMPB Control of Four Buck Stages. Here FPWM1≠ FPWM2≠ FPWM3≠ FPWM4 Buck Waveforms for -3Note Only three bucks shown here Example 3-1. Configuration for Example in Figure 500Controlling Multiple Buck Converters With Same Frequencies Control of Four Buck Stages. Note FPWM2 = N x FPWM1Buck Waveforms for -5Note FPWM2 = FPWM1 Example 3-2. Code Snippet for Configuration in Figure Controlling Multiple Half H-Bridge HHB Converters Control of Two Half-H Bridge Stages FPWM2 = N x FPWM1Half-H Bridge Waveforms for -7Note Here FPWM2 = FPWM1 Controlling Dual 3-Phase Inverters for Motors ACI and Pmsm Example 3-3. Code Snippet for Configuration in FigureEPWM1A 10 -Phase Inverter Waveforms for -9Only One Inverter Shown Example 3-4. Code Snippet for Configuration in Figure 11. Configuring Two PWM Modules for Phase Control Controlling a 3-Phase Interleaved DC/DC Converter Controlling a 3-Phase Interleaved DC/DC Converter13. Control of a 3-Phase Interleaved DC/DC Converter 14 -Phase Interleaved DC/DC Converter Waveforms for Figure Example 3-5. Code Snippet for Configuration in Figure 15. Controlling a Full-H Bridge Stage FPWM2 = FPWM1 16. ZVS Full-H Bridge Waveforms Example 3-6. Code Snippet for Configuration in Figure Submit Documentation Feedback Trip-Zone Submodule Control and Status Registers Proper Interrupt Initialization ProcedurePWM-Chopper Submodule Control Register Time-Base Period Register Tbprd Field Descriptions Time-Base Phase Register Tbphs Field DescriptionsTime-Base Submodule Registers Time-Base Counter Register Tbctr Field DescriptionsTime-Base Control Register Tbctl Field Descriptions Bit Field Value DescriptionSoftware Forced Synchronization Pulse Bit Field Counter-Compare Submodule RegistersTime-Base Status Register Tbsts Field Descriptions Bits Name Description Counter-Compare a Register Cmpa Field DescriptionsCounter-Compare B Register Cmpb Field Descriptions Action-Qualifier Submodule Registers Counter-Compare Control Register Cmpctl Field DescriptionsCBD CBD CBU CAD CAU PRD ZROBits Name 10. Action-Qualifier Output B Control Register Aqctlb Csfb Csfa Rldcsf Otsfb Actsfb Otsfa ActsfaRldcsf Inmode Polsel Outmode Dead-Band Submodule RegistersCsfb Inmode Name Value Description PWM-Chopper Submodule Control Register16. PWM-Chopper Control Register Pcctl Bit Descriptions ReservedChpduty Trip-Zone Submodule Control and Status RegistersPWM-Chopper Control Register Pcctl Bit Descriptions OSHT6 OSHT6 OSHT5 OSHT4 OSHT3 OSHT2 OSHT1CBC6 CBC5 CBC4 CBC3 CBC2 CBC1 CBC6TZB 18. Trip-Zone Control Register Tzctl Field DescriptionsTZB TZA OST CBC20. Trip-Zone Flag Register Tzflg Field Descriptions OST CBC INT22. Trip-Zone Force Register Tzfrc Field Descriptions Event-Trigger Submodule Registers21. Trip-Zone Clear Register Tzclr Field Descriptions 23. Event-Trigger Selection Register Etsel 24. Event-Trigger Prescale Register Etps Field Descriptions Name Description24. Event-Trigger Prescale Register Etps Field Descriptions Socb SocaSocb 25. Event-Trigger Flag Register Etflg Field Descriptions26. Event-Trigger Clear Register Etclr Field Descriptions Proper Interrupt Initialization Procedure 27. Event-Trigger Force Register Etfrc Field Descriptions116 Table A-1. Changes for Revision D Location Modifications, Additions, and DeletionsAppendix a Important Notice
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