Texas Instruments TMS320x28xx, 28xxx manual Example 3-5. Code Snippet for Configuration in Figure

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Controlling a 3-Phase Interleaved DC/DC Converter

Example 3-5. Code Snippet for Configuration in Figure 3-13

//=====================================================================

// Config

 

 

// Initialization Time

 

 

//========================

 

 

// EPWM Module 1 config

 

 

EPwm1Regs.TBPRD = 450;

 

// Period = 900 TBCLK counts

EPwm1Regs.TBPHS = 0;

 

// Set Phase register to zero

EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;

// Symmetrical mode

EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;

// Master module

EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;

 

EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;

// Sync down-stream module

EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;

 

EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

 

EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;

// load on CTR=Zero

EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

// load on CTR=Zero

EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;

// set actions for EPWM1A

EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;

 

EPwm1Regs.DBCTL.bit.MODE = DB_FULL_ENABLE;

// enable Dead-band module

EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;

// Active Hi complementary

EPwm1Regs.DBFED = 20;

 

// FED = 20 TBCLKs

EPwm1Regs.DBRED = 20;

 

// RED = 20 TBCLKs

// EPWM Module 2 config

 

 

EPwm2Regs.TBPRD = 450;

 

// Period = 900 TBCLK counts

EPwm2Regs.TBPHS = 300;

 

// Phase = 300/900 * 360 = 120 deg

EPwm2Regs.TBCTL.bit.CTRMODE =

TB_COUNT_UPDOWN;

// Symmetrical mode

EPwm2Regs.TBCTL.bit.PHSEN =

TB_ENABLE;

// Slave module

EPwm2Regs.TBCTL.bit.PHSDIR =

TB_DOWN;

// Count DOWN on sync (=120 deg)

EPwm2Regs.TBCTL.bit.PRDLD =

TB_SHADOW;

 

EPwm2Regs.TBCTL.bit.SYNCOSEL =

TB_SYNC_IN;

// sync flow-through

EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;

 

EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

 

EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;

// load on CTR=Zero

EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

// load on CTR=Zero

EPwm2Regs.AQCTLA.bit.CAU = AQ_SET;

// set actions for EPWM2A

EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR;

 

EPwm2Regs.DBCTL.bit.MODE = DB_FULL_ENABLE;

// enable Dead-band module

EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;

// Active Hi Complementary

EPwm2Regs.DBFED = 20;

 

// FED = 20 TBCLKs

EPwm2Regs.DBRED = 20;

 

// RED = 20 TBCLKs

// EPWM Module 3 config

 

 

EPwm3Regs.TBPRD = 450;

 

// Period = 900 TBCLK counts

EPwm3Regs.TBPHS = 300;

 

// Phase = 300/900 * 360 = 120 deg

EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;

// Symmetrical mode

EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE;

// Slave module

EPwm2Regs.TBCTL.bit.PHSDIR = TB_UP;

// Count UP on sync (=240 deg)

EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;

 

EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;

// sync flow-through

EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;

 

EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

 

EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;

// load on CTR=Zero

EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

// load on CTR=Zero

EPwm3Regs.AQCTLA.bit.CAU = AQ_SET;

// set actions for EPWM3Ai

EPwm3Regs.AQCTLA.bit.CAD = AQ_CLEAR;

 

EPwm3Regs.DBCTL.bit.MODE = DB_FULL_ENABLE;

// enable Dead-band module

EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;

// Active Hi complementary

EPwm3Regs.DBFED = 20;

 

// FED = 20 TBCLKs

EPwm3Regs.DBRED = 20;

 

// RED = 20 TBCLKs

//Run Time (Note: Example execution of one run-time instant) //===========================================================

EPwm1Regs.CMPA.half.CMPA = 285;

// adjust duty for output EPWM1A

EPwm2Regs.CMPA.half.CMPA

=

285;

// adjust duty for

output EPWM2A

EPwm3Regs.CMPA.half.CMPA

=

285;

// adjust duty for

output EPWM3A

88

Applications to Power Topologies

SPRU791D–November 2004–Revised October 2007

Page 87 Page 89
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Contents Reference Guide Submit Documentation Feedback Contents Controlling a 3-Phase Interleaved DC/DC Converter List of Figures Event-Trigger Socb Pulse Generator Simplified ePWM Module List of Tables Submit Documentation Feedback Related Documentation From Texas Instruments Data ManualsCPU Users Guides Peripheral GuidesTools Guides Application ReportsTrademarks TMS320C28x, C28x are trademarks of Texas InstrumentsSubmit Documentation Feedback Introduction Introduction Submodule OverviewMultiple ePWM Modules ∙ PWM output signals EPWMxA and EPWMxB ∙ Trip-zone signals TZ1 to TZ6∙ ADC start-of-conversion signals EPWMxSOCA and EPWMxSOCB ∙ Peripheral BusEPWM Submodules and Critical Internal Signal Interconnects Register MappingOffset Size Name DescriptionTime-Base Submodule Registers Counter-Compare Submodule RegistersEPWM Submodules Submodule Configuration Parameter or Option Submodule Configuration ParametersOverview Example 2-1. Constant Definitions Used in the Code Examples TbupChpenable Time-Base TB Submodule Purpose of the Time-Base SubmoduleTime-Base Submodule Registers Controlling and Monitoring the Time-base SubmoduleRegister Key Time-Base Signals ∙ Up-Down-Count Mode∙ Up-Count Mode ∙ Down-Count Mode∙ Time-Base Period Shadow Mode ∙ Time-Base Period Immediate Load ModeTime-Base Period Shadow Register ∙ Active RegisterTime-Base Counter Synchronization Time-Base Counter Synchronization SchemeEPWM11SYNCI EPWM11SYNCO∙ EPWMxSYNCI Synchronization Input Pulse ∙ Software Forced Synchronization PulsePhase Locking the Time-Base Clocks of Multiple ePWM Modules Time-base Counter Modes and Timing WaveformsTime-Base Down-Count Mode Waveforms Counter-Compare CC Submodule 11. Counter-Compare SubmodulePurpose of the Counter-Compare Submodule Controlling and Monitoring the Counter-Compare SubmoduleCounter-Compare Submodule Registers Register Name Address OffsetCount Mode Timing Waveforms Counter-Compare Submodule Key Signals∙ Shadow Mode ∙ Immediate Load ModeCTR=CMPA CTR=CMPBCTR = Cmpb Purpose of the Action-Qualifier Submodule Action-Qualifier AQ SubmoduleAction-Qualifier Submodule Registers Action-Qualifier Submodule Possible Input Events ∙ Set High∙ Clear Low ∙ ToggleTB Counter equals Actions Action-Qualifier Event Priority for Up-Down-Count Mode Action-Qualifier Event Priority for Up-Count Mode10. Action-Qualifier Event Priority for Down-Count Mode Action-Qualifier Event PriorityWaveforms for Common Configurations Use up-down-count mode to generate a symmetric PWMUse up-down-count mode to generate an asymmetric PWM When using up-count mode to generate an asymmetric PWM20. Up-Down-Count Mode Symmetrical Waveform Example 2-2. Code Sample for Figure TbctrValue EPWMxA EPWMxB Example 2-3. Code Sample for Figure Tbclk = SysclkoutExample 2-4. Code Sample for Figure EdgePosAExample 2-5. Code Sample for Figure Example 2-6. Code Sample for Figure TbctrExample 2-7. Code Sample for Figure EPWMxA EPWMxBDead-Band Generator DB Submodule Purpose of the Dead-Band SubmoduleControlling and Monitoring the Dead-Band Submodule 12. Dead-Band Generator Submodule Registers∙ Output Mode Control Operational Highlights for the Dead-Band Submodule∙ Input Source Selection ∙ Polarity ControlMode Description 13. Classical Dead-Band Operating Modes29. Dead-Band Waveforms for Typical Cases 0% Duty 100% Dead-Band Delay in μS FED = Dbfed × Ttbclk RED = Dbred × TtbclkPWM-Chopper PC Submodule Purpose of the PWM-Chopper SubmoduleControlling the PWM-Chopper Submodule Operational Highlights for the PWM-Chopper SubmoduleWaveforms 31. PWM-Chopper Submodule Operational Details16. Possible Pulse Width Values for Sysclkout = 100 MHz One-Shot PulseOSHTWTHz Duty Cycle Control PeriodTrip-Zone TZ Submodule Purpose of the Trip-Zone SubmoduleControlling and Monitoring the Trip-Zone Submodule Operational Highlights for the Trip-Zone Submodule17. Trip-Zone Submodule Registers ∙ Cycle-by-Cycle CBCExample 2-8. Trip-Zone Configurations 18. Possible Actions On a Trip EventScenario a Scenario B36. Trip-Zone Submodule Mode Control Logic Generating Trip Event InterruptsEvent-Trigger ET Submodule 37. Trip-Zone Submodule Interrupt LogicOperational Overview of the Event-Trigger Submodule 19. Event-Trigger Submodule Registers CTR=CMPB CTRD=CMPB41. Event-Trigger Interrupt Generator 42. Event-Trigger Soca Pulse Generator Submit Documentation Feedback Applications to Power Topologies Controlling Multiple Buck Converters With IndependentKey Configuration Capabilities Overview of Multiple ModulesCTR=0 EPWM1B CTR=CMPB Control of Four Buck Stages. Here FPWM1≠ FPWM2≠ FPWM3≠ FPWM4 Buck Waveforms for -3Note Only three bucks shown here Example 3-1. Configuration for Example in Figure 500Controlling Multiple Buck Converters With Same Frequencies Control of Four Buck Stages. Note FPWM2 = N x FPWM1Buck Waveforms for -5Note FPWM2 = FPWM1 Example 3-2. Code Snippet for Configuration in Figure Controlling Multiple Half H-Bridge HHB Converters Control of Two Half-H Bridge Stages FPWM2 = N x FPWM1Half-H Bridge Waveforms for -7Note Here FPWM2 = FPWM1 Controlling Dual 3-Phase Inverters for Motors ACI and Pmsm Example 3-3. Code Snippet for Configuration in FigureEPWM1A 10 -Phase Inverter Waveforms for -9Only One Inverter Shown Example 3-4. Code Snippet for Configuration in Figure 11. Configuring Two PWM Modules for Phase Control Controlling a 3-Phase Interleaved DC/DC Converter Controlling a 3-Phase Interleaved DC/DC Converter13. Control of a 3-Phase Interleaved DC/DC Converter 14 -Phase Interleaved DC/DC Converter Waveforms for Figure Example 3-5. Code Snippet for Configuration in Figure 15. Controlling a Full-H Bridge Stage FPWM2 = FPWM1 16. ZVS Full-H Bridge Waveforms Example 3-6. Code Snippet for Configuration in Figure Submit Documentation Feedback PWM-Chopper Submodule Control Register Proper Interrupt Initialization ProcedureTrip-Zone Submodule Control and Status Registers Time-Base Phase Register Tbphs Field Descriptions Time-Base Submodule RegistersTime-Base Period Register Tbprd Field Descriptions Time-Base Counter Register Tbctr Field DescriptionsTime-Base Control Register Tbctl Field Descriptions Bit Field Value DescriptionSoftware Forced Synchronization Pulse Time-Base Status Register Tbsts Field Descriptions Counter-Compare Submodule RegistersBit Field Counter-Compare B Register Cmpb Field Descriptions Counter-Compare a Register Cmpa Field DescriptionsBits Name Description Action-Qualifier Submodule Registers Counter-Compare Control Register Cmpctl Field DescriptionsBits Name CBD CBU CAD CAU PRD ZROCBD 10. Action-Qualifier Output B Control Register Aqctlb Rldcsf Rldcsf Otsfb Actsfb Otsfa ActsfaCsfb Csfa Csfb Dead-Band Submodule RegistersInmode Polsel Outmode Inmode PWM-Chopper Submodule Control Register 16. PWM-Chopper Control Register Pcctl Bit DescriptionsName Value Description ReservedPWM-Chopper Control Register Pcctl Bit Descriptions Trip-Zone Submodule Control and Status RegistersChpduty OSHT6 OSHT5 OSHT4 OSHT3 OSHT2 OSHT1 CBC6 CBC5 CBC4 CBC3 CBC2 CBC1OSHT6 CBC618. Trip-Zone Control Register Tzctl Field Descriptions TZB TZATZB OST CBC20. Trip-Zone Flag Register Tzflg Field Descriptions OST CBC INT21. Trip-Zone Clear Register Tzclr Field Descriptions Event-Trigger Submodule Registers22. Trip-Zone Force Register Tzfrc Field Descriptions 23. Event-Trigger Selection Register Etsel 24. Event-Trigger Prescale Register Etps Field Descriptions Name Description24. Event-Trigger Prescale Register Etps Field Descriptions Socb Soca26. Event-Trigger Clear Register Etclr Field Descriptions 25. Event-Trigger Flag Register Etflg Field DescriptionsSocb Proper Interrupt Initialization Procedure 27. Event-Trigger Force Register Etfrc Field Descriptions116 Table A-1. Changes for Revision D Location Modifications, Additions, and DeletionsAppendix a Important Notice
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