Texas Instruments TMS320x28xx, 28xxx manual Software Forced Synchronization Pulse

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Time-Base Submodule Registers

Table 4-4. Time-Base Control Register (TBCTL) Field Descriptions (continued)

Bit	Field	Value	Description
6	SWFSYNC		Software Forced Synchronization Pulse
		0	Writing a 0 has no effect and reads always return a 0.
		1	Writing a 1 forces a one-time synchronization pulse to be generated.
			This event is ORed with the EPWMxSYNCI input of the ePWM module.
			SWFSYNC is valid (operates) only when EPWMxSYNCI is selected by SYNCOSEL = 00.
5:4	SYNCOSEL		Synchronization Output Select. These bits select the source of the EPWMxSYNCO signal.
		00	EPWMxSYNC:
		01	CTR = zero: Time-base counter equal to zero (TBCTR = 0x0000)
		10	CTR = CMPB : Time-base counter equal to counter-compare B (TBCTR = CMPB)
		11	Disable EPWMxSYNCO signal
3	PRDLD		Active Period Register Load From Shadow Register Select
		0	The period register (TBPRD) is loaded from its shadow register when the time-base counter,
			TBCTR, is equal to zero.
			A write or read to the TBPRD register accesses the shadow register.
		1	Load the TBPRD register immediately without using a shadow register.
			A write or read to the TBPRD register directly accesses the active register.
2	PHSEN		Counter Register Load From Phase Register Enable
		0	Do not load the time-base counter (TBCTR) from the time-base phase register (TBPHS)
		1	Load the time-base counter with the phase register when an EPWMxSYNCI input signal occurs or
			when a software synchronization is forced by the SWFSYNC bit.
1:0	CTRMODE		Counter Mode
			The time-base counter mode is normally configured once and not changed during normal operation.
			If you change the mode of the counter, the change will take effect at the next TBCLK edge and the
			current counter value shall increment or decrement from the value before the mode change.
			These bits set the time-base counter mode of operation as follows:
		00	Up-count mode
		01	Down-count mode
		10	Up-down-count mode
		11	Stop-freeze counter operation (default on reset)

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Registers

SPRU791D–November 2004–Revised October 2007

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Contents Reference Guide Submit Documentation Feedback Contents Controlling a 3-Phase Interleaved DC/DC Converter List of Figures Event-Trigger Socb Pulse Generator Simplified ePWM Module List of Tables Submit Documentation Feedback Related Documentation From Texas Instruments Data ManualsCPU Users Guides Peripheral GuidesTools Guides Application ReportsTrademarks TMS320C28x, C28x are trademarks of Texas InstrumentsSubmit Documentation Feedback Introduction Introduction Submodule OverviewMultiple ePWM Modules ∙ PWM output signals EPWMxA and EPWMxB ∙ Trip-zone signals TZ1 to TZ6∙ ADC start-of-conversion signals EPWMxSOCA and EPWMxSOCB ∙ Peripheral BusEPWM Submodules and Critical Internal Signal Interconnects Register MappingOffset Size Name DescriptionTime-Base Submodule Registers Counter-Compare Submodule RegistersEPWM Submodules Submodule Configuration Parameters Submodule Configuration Parameter or OptionOverview Example 2-1. Constant Definitions Used in the Code Examples TbupChpenable Time-Base TB Submodule Purpose of the Time-Base SubmoduleControlling and Monitoring the Time-base Submodule Time-Base Submodule RegistersRegister Key Time-Base Signals ∙ Up-Down-Count Mode∙ Up-Count Mode ∙ Down-Count Mode∙ Time-Base Period Shadow Mode ∙ Time-Base Period Immediate Load ModeTime-Base Period Shadow Register ∙ Active RegisterTime-Base Counter Synchronization Time-Base Counter Synchronization SchemeEPWM11SYNCI EPWM11SYNCO∙ EPWMxSYNCI Synchronization Input Pulse ∙ Software Forced Synchronization PulsePhase Locking the Time-Base Clocks of Multiple ePWM Modules Time-base Counter Modes and Timing WaveformsTime-Base Down-Count Mode Waveforms Counter-Compare CC Submodule 11. Counter-Compare SubmodulePurpose of the Counter-Compare Submodule Controlling and Monitoring the Counter-Compare SubmoduleCounter-Compare Submodule Registers Register Name Address OffsetCount Mode Timing Waveforms Counter-Compare Submodule Key Signals∙ Shadow Mode ∙ Immediate Load ModeCTR=CMPA CTR=CMPBCTR = Cmpb Action-Qualifier AQ Submodule Purpose of the Action-Qualifier SubmoduleAction-Qualifier Submodule Registers Action-Qualifier Submodule Possible Input Events ∙ Set High∙ Clear Low ∙ ToggleTB Counter equals Actions Action-Qualifier Event Priority for Up-Down-Count Mode Action-Qualifier Event Priority for Up-Count Mode10. Action-Qualifier Event Priority for Down-Count Mode Action-Qualifier Event PriorityWaveforms for Common Configurations Use up-down-count mode to generate a symmetric PWMUse up-down-count mode to generate an asymmetric PWM When using up-count mode to generate an asymmetric PWM20. Up-Down-Count Mode Symmetrical Waveform Example 2-2. Code Sample for Figure TbctrValue EPWMxA EPWMxB Example 2-3. Code Sample for Figure Tbclk = SysclkoutExample 2-4. Code Sample for Figure EdgePosAExample 2-5. Code Sample for Figure Example 2-6. Code Sample for Figure TbctrExample 2-7. Code Sample for Figure EPWMxA EPWMxBDead-Band Generator DB Submodule Purpose of the Dead-Band SubmoduleControlling and Monitoring the Dead-Band Submodule 12. Dead-Band Generator Submodule Registers∙ Output Mode Control Operational Highlights for the Dead-Band Submodule∙ Input Source Selection ∙ Polarity ControlMode Description 13. Classical Dead-Band Operating Modes29. Dead-Band Waveforms for Typical Cases 0% Duty 100% Dead-Band Delay in μS FED = Dbfed × Ttbclk RED = Dbred × TtbclkPWM-Chopper PC Submodule Purpose of the PWM-Chopper SubmoduleControlling the PWM-Chopper Submodule Operational Highlights for the PWM-Chopper SubmoduleWaveforms 31. PWM-Chopper Submodule Operational DetailsOne-Shot Pulse 16. Possible Pulse Width Values for Sysclkout = 100 MHzOSHTWTHz Duty Cycle Control PeriodTrip-Zone TZ Submodule Purpose of the Trip-Zone SubmoduleControlling and Monitoring the Trip-Zone Submodule Operational Highlights for the Trip-Zone Submodule17. Trip-Zone Submodule Registers ∙ Cycle-by-Cycle CBCExample 2-8. Trip-Zone Configurations 18. Possible Actions On a Trip EventScenario a Scenario B36. Trip-Zone Submodule Mode Control Logic Generating Trip Event InterruptsEvent-Trigger ET Submodule 37. Trip-Zone Submodule Interrupt LogicOperational Overview of the Event-Trigger Submodule 19. Event-Trigger Submodule Registers CTR=CMPB CTRD=CMPB41. Event-Trigger Interrupt Generator 42. Event-Trigger Soca Pulse Generator Submit Documentation Feedback Applications to Power Topologies Controlling Multiple Buck Converters With IndependentKey Configuration Capabilities Overview of Multiple ModulesCTR=0 EPWM1B CTR=CMPB Control of Four Buck Stages. Here FPWM1≠ FPWM2≠ FPWM3≠ FPWM4 Buck Waveforms for -3Note Only three bucks shown here Example 3-1. Configuration for Example in Figure 500Controlling Multiple Buck Converters With Same Frequencies Control of Four Buck Stages. Note FPWM2 = N x FPWM1Buck Waveforms for -5Note FPWM2 = FPWM1 Example 3-2. Code Snippet for Configuration in Figure Controlling Multiple Half H-Bridge HHB Converters Control of Two Half-H Bridge Stages FPWM2 = N x FPWM1Half-H Bridge Waveforms for -7Note Here FPWM2 = FPWM1 Controlling Dual 3-Phase Inverters for Motors ACI and Pmsm Example 3-3. Code Snippet for Configuration in FigureEPWM1A 10 -Phase Inverter Waveforms for -9Only One Inverter Shown Example 3-4. Code Snippet for Configuration in Figure 11. Configuring Two PWM Modules for Phase Control Controlling a 3-Phase Interleaved DC/DC Converter Controlling a 3-Phase Interleaved DC/DC Converter13. Control of a 3-Phase Interleaved DC/DC Converter 14 -Phase Interleaved DC/DC Converter Waveforms for Figure Example 3-5. Code Snippet for Configuration in Figure 15. Controlling a Full-H Bridge Stage FPWM2 = FPWM1 16. ZVS Full-H Bridge Waveforms Example 3-6. Code Snippet for Configuration in Figure Submit Documentation Feedback Proper Interrupt Initialization Procedure PWM-Chopper Submodule Control RegisterTrip-Zone Submodule Control and Status Registers Time-Base Phase Register Tbphs Field Descriptions Time-Base Submodule RegistersTime-Base Period Register Tbprd Field Descriptions Time-Base Counter Register Tbctr Field DescriptionsTime-Base Control Register Tbctl Field Descriptions Bit Field Value DescriptionSoftware Forced Synchronization Pulse Counter-Compare Submodule Registers Time-Base Status Register Tbsts Field DescriptionsBit Field Counter-Compare a Register Cmpa Field Descriptions Counter-Compare B Register Cmpb Field DescriptionsBits Name Description Action-Qualifier Submodule Registers Counter-Compare Control Register Cmpctl Field DescriptionsCBD CBU CAD CAU PRD ZRO Bits NameCBD 10. Action-Qualifier Output B Control Register Aqctlb Rldcsf Otsfb Actsfb Otsfa Actsfa RldcsfCsfb Csfa Dead-Band Submodule Registers CsfbInmode Polsel Outmode Inmode PWM-Chopper Submodule Control Register 16. PWM-Chopper Control Register Pcctl Bit DescriptionsName Value Description ReservedTrip-Zone Submodule Control and Status Registers PWM-Chopper Control Register Pcctl Bit DescriptionsChpduty OSHT6 OSHT5 OSHT4 OSHT3 OSHT2 OSHT1 CBC6 CBC5 CBC4 CBC3 CBC2 CBC1OSHT6 CBC618. Trip-Zone Control Register Tzctl Field Descriptions TZB TZATZB OST CBC20. Trip-Zone Flag Register Tzflg Field Descriptions OST CBC INTEvent-Trigger Submodule Registers 21. Trip-Zone Clear Register Tzclr Field Descriptions22. Trip-Zone Force Register Tzfrc Field Descriptions 23. Event-Trigger Selection Register Etsel 24. Event-Trigger Prescale Register Etps Field Descriptions Name Description24. Event-Trigger Prescale Register Etps Field Descriptions Socb Soca25. Event-Trigger Flag Register Etflg Field Descriptions 26. Event-Trigger Clear Register Etclr Field DescriptionsSocb Proper Interrupt Initialization Procedure 27. Event-Trigger Force Register Etfrc Field Descriptions116 Table A-1. Changes for Revision D Location Modifications, Additions, and DeletionsAppendix a Important Notice