Texas Instruments 28xxx, TMS320x28xx manual Time-Base Control Register Tbctl Field Descriptions

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Time-Base Submodule Registers

Figure 4-4. Time-Base Control Register (TBCTL)

15	14	13	12		10	9	8
FREE, SOFT		PHSDIR		CLKDIV			HSPCLKDIV
R/W-0		R/W-0		R/W-0			R/W-0,0,1
7	6	5	4	3	2	1	0
HSPCLKDIV	SWFSYNC	SYNCOSEL		PRDLD	PHSEN		CTRMODE
R/W-0,0,1	R/W-0	R/W-0		R/W-0	R/W-0		R/W-11
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-4. Time-Base Control Register (TBCTL) Field Descriptions

Bit	Field	Value	Description
15:14	FREE, SOFT		Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during
			emulation events:
		00	Stop after the next time-base counter increment or decrement
		01	Stop when counter completes a whole cycle:
			∙	Up-count mode: stop when the time-base counter = period (TBCTR = TBPRD)
			∙	Down-count mode: stop when the time-base counter = 0x0000 (TBCTR = 0x0000)
			∙	Up-down-count mode: stop when the time-base counter = 0x0000 (TBCTR = 0x0000)
		1X	Free run
13	PHSDIR		Phase Direction Bit.
			This bit is only used when the time-base counter is configured in the up-down-count mode. The
			PHSDIR bit indicates the direction the time-base counter (TBCTR) will count after a synchronization
			event occurs and a new phase value is loaded from the phase (TBPHS) register. This is
			irrespective of the direction of the counter before the synchronization event..
			In the up-count and down-count modes this bit is ignored.
		0	Count down after the synchronization event.
		1	Count up after the synchronization event.
12:10	CLKDIV		Time-base Clock Prescale Bits
			These bits determine part of the time-base clock prescale value.
			TBCLK = SYSCLKOUT / (HSPCLKDIV × CLKDIV)
		000	/1 (default on reset)
		001	/2
		010	/4
		011	/8
		100	/16
		101	/32
		110	/64
		111	/128
9:7	HSPCLKDIV		High Speed Time-base Clock Prescale Bits
			These bits determine part of the time-base clock prescale value.
			TBCLK = SYSCLKOUT / (HSPCLKDIV × CLKDIV)
			This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager
			(EV) peripheral.
		000	/1
		001	/2 (default on reset)
		010	/4
		011	/6
		100	/8
		101	/10
		110	/12
		111	/14
SPRU791D–November 2004–Revised October 2007					Registers	95

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Contents Reference Guide Submit Documentation Feedback Contents Controlling a 3-Phase Interleaved DC/DC Converter List of Figures Event-Trigger Socb Pulse Generator Simplified ePWM Module List of Tables Submit Documentation Feedback Peripheral Guides Related Documentation From Texas InstrumentsData Manuals CPU Users GuidesApplication Reports Tools GuidesTMS320C28x, C28x are trademarks of Texas Instruments TrademarksSubmit Documentation Feedback Introduction Submodule Overview IntroductionMultiple ePWM Modules ∙ Peripheral Bus ∙ PWM output signals EPWMxA and EPWMxB∙ Trip-zone signals TZ1 to TZ6 ∙ ADC start-of-conversion signals EPWMxSOCA and EPWMxSOCBRegister Mapping EPWM Submodules and Critical Internal Signal InterconnectsCounter-Compare Submodule Registers Offset Size NameDescription Time-Base Submodule RegistersEPWM Submodules Overview Submodule Configuration ParametersSubmodule Configuration Parameter or Option Tbup Example 2-1. Constant Definitions Used in the Code ExamplesChpenable Purpose of the Time-Base Submodule Time-Base TB SubmoduleRegister Controlling and Monitoring the Time-base SubmoduleTime-Base Submodule Registers ∙ Down-Count Mode Key Time-Base Signals∙ Up-Down-Count Mode ∙ Up-Count Mode∙ Active Register ∙ Time-Base Period Shadow Mode∙ Time-Base Period Immediate Load Mode Time-Base Period Shadow RegisterTime-Base Counter Synchronization Scheme Time-Base Counter SynchronizationEPWM11SYNCO EPWM11SYNCI∙ Software Forced Synchronization Pulse ∙ EPWMxSYNCI Synchronization Input PulseTime-base Counter Modes and Timing Waveforms Phase Locking the Time-Base Clocks of Multiple ePWM ModulesTime-Base Down-Count Mode Waveforms 11. Counter-Compare Submodule Counter-Compare CC SubmoduleRegister Name Address Offset Purpose of the Counter-Compare SubmoduleControlling and Monitoring the Counter-Compare Submodule Counter-Compare Submodule Registers∙ Immediate Load Mode Count Mode Timing WaveformsCounter-Compare Submodule Key Signals ∙ Shadow ModeCTR=CMPB CTR=CMPACTR = Cmpb Action-Qualifier Submodule Registers Action-Qualifier AQ SubmodulePurpose of the Action-Qualifier Submodule ∙ Toggle Action-Qualifier Submodule Possible Input Events∙ Set High ∙ Clear LowTB Counter equals Actions Action-Qualifier Event Priority Action-Qualifier Event Priority for Up-Down-Count ModeAction-Qualifier Event Priority for Up-Count Mode 10. Action-Qualifier Event Priority for Down-Count ModeWhen using up-count mode to generate an asymmetric PWM Waveforms for Common ConfigurationsUse up-down-count mode to generate a symmetric PWM Use up-down-count mode to generate an asymmetric PWM20. Up-Down-Count Mode Symmetrical Waveform Tbctr Example 2-2. Code Sample for FigureValue EPWMxA EPWMxB Tbclk = Sysclkout Example 2-3. Code Sample for FigureEdgePosA Example 2-4. Code Sample for FigureExample 2-5. Code Sample for Figure Tbctr Example 2-6. Code Sample for FigureEPWMxA EPWMxB Example 2-7. Code Sample for Figure12. Dead-Band Generator Submodule Registers Dead-Band Generator DB SubmodulePurpose of the Dead-Band Submodule Controlling and Monitoring the Dead-Band Submodule∙ Polarity Control ∙ Output Mode ControlOperational Highlights for the Dead-Band Submodule ∙ Input Source Selection13. Classical Dead-Band Operating Modes Mode Description29. Dead-Band Waveforms for Typical Cases 0% Duty 100% FED = Dbfed × Ttbclk RED = Dbred × Ttbclk Dead-Band Delay in μSOperational Highlights for the PWM-Chopper Submodule PWM-Chopper PC SubmodulePurpose of the PWM-Chopper Submodule Controlling the PWM-Chopper Submodule31. PWM-Chopper Submodule Operational Details WaveformsOSHTWTHz One-Shot Pulse16. Possible Pulse Width Values for Sysclkout = 100 MHz Period Duty Cycle ControlPurpose of the Trip-Zone Submodule Trip-Zone TZ Submodule∙ Cycle-by-Cycle CBC Controlling and Monitoring the Trip-Zone SubmoduleOperational Highlights for the Trip-Zone Submodule 17. Trip-Zone Submodule RegistersScenario B Example 2-8. Trip-Zone Configurations18. Possible Actions On a Trip Event Scenario aGenerating Trip Event Interrupts 36. Trip-Zone Submodule Mode Control Logic37. Trip-Zone Submodule Interrupt Logic Event-Trigger ET SubmoduleOperational Overview of the Event-Trigger Submodule CTR=CMPB CTRD=CMPB 19. Event-Trigger Submodule Registers41. Event-Trigger Interrupt Generator 42. Event-Trigger Soca Pulse Generator Submit Documentation Feedback Controlling Multiple Buck Converters With Independent Applications to Power TopologiesOverview of Multiple Modules Key Configuration CapabilitiesCTR=0 EPWM1B CTR=CMPB Control of Four Buck Stages. Here FPWM1≠ FPWM2≠ FPWM3≠ FPWM4 Buck Waveforms for -3Note Only three bucks shown here 500 Example 3-1. Configuration for Example in FigureControl of Four Buck Stages. Note FPWM2 = N x FPWM1 Controlling Multiple Buck Converters With Same FrequenciesBuck Waveforms for -5Note FPWM2 = FPWM1 Example 3-2. Code Snippet for Configuration in Figure Control of Two Half-H Bridge Stages FPWM2 = N x FPWM1 Controlling Multiple Half H-Bridge HHB ConvertersHalf-H Bridge Waveforms for -7Note Here FPWM2 = FPWM1 Example 3-3. Code Snippet for Configuration in Figure Controlling Dual 3-Phase Inverters for Motors ACI and PmsmEPWM1A 10 -Phase Inverter Waveforms for -9Only One Inverter Shown Example 3-4. Code Snippet for Configuration in Figure 11. Configuring Two PWM Modules for Phase Control Controlling a 3-Phase Interleaved DC/DC Converter Controlling a 3-Phase Interleaved DC/DC Converter13. Control of a 3-Phase Interleaved DC/DC Converter 14 -Phase Interleaved DC/DC Converter Waveforms for Figure Example 3-5. Code Snippet for Configuration in Figure 15. Controlling a Full-H Bridge Stage FPWM2 = FPWM1 16. ZVS Full-H Bridge Waveforms Example 3-6. Code Snippet for Configuration in Figure Submit Documentation Feedback Trip-Zone Submodule Control and Status Registers Proper Interrupt Initialization ProcedurePWM-Chopper Submodule Control Register Time-Base Counter Register Tbctr Field Descriptions Time-Base Phase Register Tbphs Field DescriptionsTime-Base Submodule Registers Time-Base Period Register Tbprd Field DescriptionsBit Field Value Description Time-Base Control Register Tbctl Field DescriptionsSoftware Forced Synchronization Pulse Bit Field Counter-Compare Submodule RegistersTime-Base Status Register Tbsts Field Descriptions Bits Name Description Counter-Compare a Register Cmpa Field DescriptionsCounter-Compare B Register Cmpb Field Descriptions Counter-Compare Control Register Cmpctl Field Descriptions Action-Qualifier Submodule RegistersCBD CBD CBU CAD CAU PRD ZROBits Name 10. Action-Qualifier Output B Control Register Aqctlb Csfb Csfa Rldcsf Otsfb Actsfb Otsfa ActsfaRldcsf Inmode Polsel Outmode Dead-Band Submodule RegistersCsfb Inmode Reserved PWM-Chopper Submodule Control Register16. PWM-Chopper Control Register Pcctl Bit Descriptions Name Value DescriptionChpduty Trip-Zone Submodule Control and Status RegistersPWM-Chopper Control Register Pcctl Bit Descriptions CBC6 OSHT6 OSHT5 OSHT4 OSHT3 OSHT2 OSHT1CBC6 CBC5 CBC4 CBC3 CBC2 CBC1 OSHT6OST CBC 18. Trip-Zone Control Register Tzctl Field DescriptionsTZB TZA TZBOST CBC INT 20. Trip-Zone Flag Register Tzflg Field Descriptions22. Trip-Zone Force Register Tzfrc Field Descriptions Event-Trigger Submodule Registers21. Trip-Zone Clear Register Tzclr Field Descriptions 23. Event-Trigger Selection Register Etsel Name Description 24. Event-Trigger Prescale Register Etps Field DescriptionsSocb Soca 24. Event-Trigger Prescale Register Etps Field DescriptionsSocb 25. Event-Trigger Flag Register Etflg Field Descriptions26. Event-Trigger Clear Register Etclr Field Descriptions 27. Event-Trigger Force Register Etfrc Field Descriptions Proper Interrupt Initialization Procedure116 Location Modifications, Additions, and Deletions Table A-1. Changes for Revision DAppendix a Important Notice