Texas Instruments 28xxx, TMS320x28xx Calculating PWM Period and Frequency, Key Time-Base Signals

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Time-Base (TB) Submodule

 

Table 2-3. Key Time-Base Signals

Signal

Description

EPWMxSYNCI

Time-base synchronization input.

 

Input pulse used to synchronize the time-base counter with the counter of ePWM module earlier in the

 

synchronization chain. An ePWM peripheral can be configured to use or ignore this signal. For the first ePWM

 

module (EPWM1) this signal comes from a device pin. For subsequent ePWM modules this signal is passed

 

from another ePWM peripheral. For example, EPWM2SYNCI is generated by the ePWM1 peripheral,

 

EPWM3SYNCI is generated by ePWM2 and so forth. See Section 2.2.3.2 for information on the

 

synchronization order of a particular device.

EPWMxSYNCO

Time-base synchronization output.

 

This output pulse is used to synchronize the counter of an ePWM module later in the synchronization chain.

 

The ePWM module generates this signal from one of three event sources:

 

1. EPWMxSYNCI (Synchronization input pulse)

 

2. CTR = Zero: The time-base counter equal to zero (TBCTR = 0x0000).

 

3. CTR = CMPB: The time-base counter equal to the counter-compare B (TBCTR = CMPB) register.

CTR = PRD

Time-base counter equal to the specified period.

 

This signal is generated whenever the counter value is equal to the active period register value. That is when

 

TBCTR = TBPRD.

CTR = Zero

Time-base counter equal to zero

 

This signal is generated whenever the counter value is zero. That is when TBCTR equals 0x0000.

CTR = CMPB

Time-base counter equal to active counter-compare B register (TBCTR = CMPB).

 

This event is generated by the counter-compare submodule and used by the synchronization out logic

CTR_dir

Time-base counter direction.

 

Indicates the current direction of the ePWM's time-base counter. This signal is high when the counter is

 

increasing and low when it is decreasing.

CTR_max

Time-base counter equal max value. (TBCTR = 0xFFFF)

 

Generated event when the TBCTR value reaches its maximum value. This signal is only used only as a status

 

bit

TBCLK

Time-base clock.

 

This is a prescaled version of the system clock (SYSCLKOUT) and is used by all submodules within the

 

ePWM. This clock determines the rate at which time-base counter increments or decrements.

2.2.3 Calculating PWM Period and Frequency

The frequency of PWM events is controlled by the time-base period (TBPRD) register and the mode of the time-base counter. Figure 2-3shows the period (Tpwm) and frequency (Fpwm) relationships for the up-count, down-count, and up-down-count time-base counter modes when when the period is set to 4 (TBPRD = 4). The time increment for each step is defined by the time-base clock (TBCLK) which is a prescaled version of the system clock (SYSCLKOUT).

The time-base counter has three modes of operation selected by the time-base control register (TBCTL):

∙Up-Down-Count Mode:

In up-down-count mode, the time-base counter starts from zero and increments until the period (TBPRD) value is reached. When the period value is reached, the time-base counter then decrements until it reaches zero. At this point the counter repeats the pattern and begins to increment.

∙Up-Count Mode:

In this mode, the time-base counter starts from zero and increments until it reaches the value in the period register (TBPRD). When the period value is reached, the time-base counter resets to zero and begins to increment once again.

∙Down-Count Mode:

In down-count mode, the time-base counter starts from the period (TBPRD) value and decrements until it reaches zero. When it reaches zero, the time-base counter is reset to the period value and it begins to decrement once again.

SPRU791D–November 2004–Revised October 2007

ePWM Submodules

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Contents Reference Guide Submit Documentation Feedback Contents Controlling a 3-Phase Interleaved DC/DC Converter List of Figures Event-Trigger Socb Pulse Generator Simplified ePWM Module List of Tables Submit Documentation Feedback Data Manuals Related Documentation From Texas InstrumentsCPU Users Guides Peripheral GuidesApplication Reports Tools GuidesTMS320C28x, C28x are trademarks of Texas Instruments TrademarksSubmit Documentation Feedback Introduction Submodule Overview IntroductionMultiple ePWM Modules ∙ Trip-zone signals TZ1 to TZ6 ∙ PWM output signals EPWMxA and EPWMxB∙ ADC start-of-conversion signals EPWMxSOCA and EPWMxSOCB ∙ Peripheral BusRegister Mapping EPWM Submodules and Critical Internal Signal InterconnectsDescription Offset Size NameTime-Base Submodule Registers Counter-Compare Submodule RegistersEPWM Submodules Submodule Configuration Parameter or Option Submodule Configuration ParametersOverview Tbup Example 2-1. Constant Definitions Used in the Code Examples Chpenable Purpose of the Time-Base Submodule Time-Base TB SubmoduleTime-Base Submodule Registers Controlling and Monitoring the Time-base SubmoduleRegister ∙ Up-Down-Count Mode Key Time-Base Signals∙ Up-Count Mode ∙ Down-Count Mode∙ Time-Base Period Immediate Load Mode ∙ Time-Base Period Shadow ModeTime-Base Period Shadow Register ∙ Active RegisterTime-Base Counter Synchronization Scheme Time-Base Counter SynchronizationEPWM11SYNCO EPWM11SYNCI∙ Software Forced Synchronization Pulse ∙ EPWMxSYNCI Synchronization Input PulseTime-base Counter Modes and Timing Waveforms Phase Locking the Time-Base Clocks of Multiple ePWM ModulesTime-Base Down-Count Mode Waveforms 11. Counter-Compare Submodule Counter-Compare CC SubmoduleControlling and Monitoring the Counter-Compare Submodule Purpose of the Counter-Compare SubmoduleCounter-Compare Submodule Registers Register Name Address OffsetCounter-Compare Submodule Key Signals Count Mode Timing Waveforms∙ Shadow Mode ∙ Immediate Load ModeCTR=CMPB CTR=CMPACTR = Cmpb Purpose of the Action-Qualifier Submodule Action-Qualifier AQ SubmoduleAction-Qualifier Submodule Registers ∙ Set High Action-Qualifier Submodule Possible Input Events∙ Clear Low ∙ ToggleTB Counter equals Actions Action-Qualifier Event Priority for Up-Count Mode Action-Qualifier Event Priority for Up-Down-Count Mode10. Action-Qualifier Event Priority for Down-Count Mode Action-Qualifier Event PriorityUse up-down-count mode to generate a symmetric PWM Waveforms for Common ConfigurationsUse up-down-count mode to generate an asymmetric PWM When using up-count mode to generate an asymmetric PWM20. Up-Down-Count Mode Symmetrical Waveform Tbctr Example 2-2. Code Sample for FigureValue EPWMxA EPWMxB Tbclk = Sysclkout Example 2-3. Code Sample for FigureEdgePosA Example 2-4. Code Sample for FigureExample 2-5. Code Sample for Figure Tbctr Example 2-6. Code Sample for FigureEPWMxA EPWMxB Example 2-7. Code Sample for FigurePurpose of the Dead-Band Submodule Dead-Band Generator DB SubmoduleControlling and Monitoring the Dead-Band Submodule 12. Dead-Band Generator Submodule RegistersOperational Highlights for the Dead-Band Submodule ∙ Output Mode Control∙ Input Source Selection ∙ Polarity Control13. Classical Dead-Band Operating Modes Mode Description29. Dead-Band Waveforms for Typical Cases 0% Duty 100% FED = Dbfed × Ttbclk RED = Dbred × Ttbclk Dead-Band Delay in μSPurpose of the PWM-Chopper Submodule PWM-Chopper PC SubmoduleControlling the PWM-Chopper Submodule Operational Highlights for the PWM-Chopper Submodule31. PWM-Chopper Submodule Operational Details Waveforms16. Possible Pulse Width Values for Sysclkout = 100 MHz One-Shot PulseOSHTWTHz Period Duty Cycle ControlPurpose of the Trip-Zone Submodule Trip-Zone TZ SubmoduleOperational Highlights for the Trip-Zone Submodule Controlling and Monitoring the Trip-Zone Submodule17. Trip-Zone Submodule Registers ∙ Cycle-by-Cycle CBC18. Possible Actions On a Trip Event Example 2-8. Trip-Zone ConfigurationsScenario a Scenario BGenerating Trip Event Interrupts 36. Trip-Zone Submodule Mode Control Logic37. Trip-Zone Submodule Interrupt Logic Event-Trigger ET SubmoduleOperational Overview of the Event-Trigger Submodule CTR=CMPB CTRD=CMPB 19. Event-Trigger Submodule Registers41. Event-Trigger Interrupt Generator 42. Event-Trigger Soca Pulse Generator Submit Documentation Feedback Controlling Multiple Buck Converters With Independent Applications to Power TopologiesOverview of Multiple Modules Key Configuration CapabilitiesCTR=0 EPWM1B CTR=CMPB Control of Four Buck Stages. Here FPWM1≠ FPWM2≠ FPWM3≠ FPWM4 Buck Waveforms for -3Note Only three bucks shown here 500 Example 3-1. Configuration for Example in FigureControl of Four Buck Stages. Note FPWM2 = N x FPWM1 Controlling Multiple Buck Converters With Same FrequenciesBuck Waveforms for -5Note FPWM2 = FPWM1 Example 3-2. Code Snippet for Configuration in Figure Control of Two Half-H Bridge Stages FPWM2 = N x FPWM1 Controlling Multiple Half H-Bridge HHB ConvertersHalf-H Bridge Waveforms for -7Note Here FPWM2 = FPWM1 Example 3-3. Code Snippet for Configuration in Figure Controlling Dual 3-Phase Inverters for Motors ACI and PmsmEPWM1A 10 -Phase Inverter Waveforms for -9Only One Inverter Shown Example 3-4. Code Snippet for Configuration in Figure 11. Configuring Two PWM Modules for Phase Control Controlling a 3-Phase Interleaved DC/DC Converter Controlling a 3-Phase Interleaved DC/DC Converter13. Control of a 3-Phase Interleaved DC/DC Converter 14 -Phase Interleaved DC/DC Converter Waveforms for Figure Example 3-5. Code Snippet for Configuration in Figure 15. Controlling a Full-H Bridge Stage FPWM2 = FPWM1 16. ZVS Full-H Bridge Waveforms Example 3-6. Code Snippet for Configuration in Figure Submit Documentation Feedback PWM-Chopper Submodule Control Register Proper Interrupt Initialization ProcedureTrip-Zone Submodule Control and Status Registers Time-Base Submodule Registers Time-Base Phase Register Tbphs Field DescriptionsTime-Base Period Register Tbprd Field Descriptions Time-Base Counter Register Tbctr Field DescriptionsBit Field Value Description Time-Base Control Register Tbctl Field DescriptionsSoftware Forced Synchronization Pulse Time-Base Status Register Tbsts Field Descriptions Counter-Compare Submodule RegistersBit Field Counter-Compare B Register Cmpb Field Descriptions Counter-Compare a Register Cmpa Field DescriptionsBits Name Description Counter-Compare Control Register Cmpctl Field Descriptions Action-Qualifier Submodule RegistersBits Name CBD CBU CAD CAU PRD ZROCBD 10. Action-Qualifier Output B Control Register Aqctlb Rldcsf Rldcsf Otsfb Actsfb Otsfa ActsfaCsfb Csfa Csfb Dead-Band Submodule RegistersInmode Polsel Outmode Inmode 16. PWM-Chopper Control Register Pcctl Bit Descriptions PWM-Chopper Submodule Control RegisterName Value Description ReservedPWM-Chopper Control Register Pcctl Bit Descriptions Trip-Zone Submodule Control and Status RegistersChpduty CBC6 CBC5 CBC4 CBC3 CBC2 CBC1 OSHT6 OSHT5 OSHT4 OSHT3 OSHT2 OSHT1OSHT6 CBC6TZB TZA 18. Trip-Zone Control Register Tzctl Field DescriptionsTZB OST CBCOST CBC INT 20. Trip-Zone Flag Register Tzflg Field Descriptions21. Trip-Zone Clear Register Tzclr Field Descriptions Event-Trigger Submodule Registers22. Trip-Zone Force Register Tzfrc Field Descriptions 23. Event-Trigger Selection Register Etsel Name Description 24. Event-Trigger Prescale Register Etps Field DescriptionsSocb Soca 24. Event-Trigger Prescale Register Etps Field Descriptions26. Event-Trigger Clear Register Etclr Field Descriptions 25. Event-Trigger Flag Register Etflg Field DescriptionsSocb 27. Event-Trigger Force Register Etfrc Field Descriptions Proper Interrupt Initialization Procedure116 Location Modifications, Additions, and Deletions Table A-1. Changes for Revision DAppendix a Important Notice
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