Texas Instruments TMS320x28xx Controlling and Monitoring the Trip-Zone Submodule, ∙ One-Shot Osht

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Trip-Zone (TZ) Submodule

2.7.2 Controlling and Monitoring the Trip-Zone Submodule

The trip-zone submodule operation is controlled and monitored through the following registers:

Table 2-17. Trip-Zone Submodule Registers

Register Name

Address offset

Shadowed

Description (1)

TZSEL

0x0012

No

Trip-Zone Select Register

reserved

0x0013

 

 

TZCTL

0x0014

No

Trip-Zone Control Register

TZEINT

0x0015

No

Trip-Zone Enable Interrupt Register

TZFLG

0x0016

No

Trip-Zone Flag Register

TZCLR

0x0017

No

Trip-Zone Clear Register

TZFRC

0x0018

No

Trip-Zone Force Register

(1)All trip-zone registers are EALLOW protected and can be modified only after executing the EALLOW instruction. For more information, see the device-specific version of the System Control and Interrupts Reference Guide listed in Section 1.

2.7.3Operational Highlights for the Trip-Zone Submodule

The following sections describe the operational highlights and configuration options for the trip-zone submodule.

The trip-zone signals at pins TZ1 to TZ6 (also collectively referred to as TZn) are active low input signals. When one of these pins goes low, it indicates that a trip event has occurred. Each ePWM module can be individually configured to ignore or use each of the trip-zone pins. Which trip-zone pins are used by a particular ePWM module is determined by the TZSEL register for that specific ePWM module. The trip-zone signals may or may not be synchronized to the system clock (SYSCLKOUT) and digitally filtered within the GPIO MUX block. A minimum 1 SYSCLKOUT low pulse on TZn inputs is sufficient to trigger a fault condition in the ePWM module. The asynchronous trip makes sure that if clocks are missing for any reason, the outputs can still be tripped by a valid event present on TZn inputs, providing the GPIO is appropriately configured. For more information, see the GPIO section of the specific device version of the System Control and Interrupts Reference Guide listed in Section 1.

Each TZn input can be individually configured to provide either a cycle-by-cycle or one-shot trip event for a ePWM module. The configuration is determined by the TZSEL[CBCn] and TZSEL[OSHTn] control bits (where n corresponds to the trip pin) respectively.

∙Cycle-by-Cycle (CBC):

When a cycle-by-cycle trip event occurs, the action specified in the TZCTL register is carried out immediately on the EPWMxA and/or EPWMxB output. Table 2-18lists the possible actions. In addition, the cycle-by-cycle trip event flag (TZFLG[CBC]) is set and a EPWMx_TZINT interrupt is generated if it is enabled in the TZEINT register and PIE peripheral.

The specified condition on the pins is automatically cleared when the ePWM time-base counter reaches zero (TBCTR = 0x0000) if the trip event is no longer present. Therefore, in this mode, the trip event is cleared or reset every PWM cycle. The TZFLG[CBC] flag bit will remain set until it is manually cleared by writing to the TZCLR[CBC] bit. If the cycle-by-cycle trip event is still present when the TZFLG[CBC] bit is cleared, then it will again be immediately set.

∙One-Shot (OSHT):

When a one-shot trip event occurs, the action specified in the TZCTL register is carried out immediately on the EPWMxA and/or EPWMxB output. Table 2-18lists the possible actions. In addition, the one-shot trip event flag (TZFLG[OST]) is set and a EPWMx_TZINT interrupt is generated if it is enabled in the TZEINT register and PIE peripheral. The one-shot trip condition must be cleared manually by writing to the TZCLR[OST] bit.

The action taken when a trip event occurs can be configured individually for each of the ePWM output pins by way of the TZCTL[TZA] and TZCTL[TZB] register bits. One of four possible actions, shown in Table 2-18, can be taken on a trip event.

60

ePWM Submodules

SPRU791D–November 2004–Revised October 2007

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Contents Reference Guide Submit Documentation Feedback Contents Controlling a 3-Phase Interleaved DC/DC Converter List of Figures Event-Trigger Socb Pulse Generator Simplified ePWM Module List of Tables Submit Documentation Feedback Related Documentation From Texas Instruments Data ManualsCPU Users Guides Peripheral GuidesTools Guides Application ReportsTrademarks TMS320C28x, C28x are trademarks of Texas InstrumentsSubmit Documentation Feedback Introduction Introduction Submodule OverviewMultiple ePWM Modules ∙ PWM output signals EPWMxA and EPWMxB ∙ Trip-zone signals TZ1 to TZ6∙ ADC start-of-conversion signals EPWMxSOCA and EPWMxSOCB ∙ Peripheral BusEPWM Submodules and Critical Internal Signal Interconnects Register MappingOffset Size Name DescriptionTime-Base Submodule Registers Counter-Compare Submodule RegistersEPWM Submodules Submodule Configuration Parameters Submodule Configuration Parameter or OptionOverview Example 2-1. Constant Definitions Used in the Code Examples TbupChpenable Time-Base TB Submodule Purpose of the Time-Base SubmoduleControlling and Monitoring the Time-base Submodule Time-Base Submodule RegistersRegister Key Time-Base Signals ∙ Up-Down-Count Mode∙ Up-Count Mode ∙ Down-Count Mode∙ Time-Base Period Shadow Mode ∙ Time-Base Period Immediate Load ModeTime-Base Period Shadow Register ∙ Active RegisterTime-Base Counter Synchronization Time-Base Counter Synchronization SchemeEPWM11SYNCI EPWM11SYNCO∙ EPWMxSYNCI Synchronization Input Pulse ∙ Software Forced Synchronization PulsePhase Locking the Time-Base Clocks of Multiple ePWM Modules Time-base Counter Modes and Timing WaveformsTime-Base Down-Count Mode Waveforms Counter-Compare CC Submodule 11. Counter-Compare SubmodulePurpose of the Counter-Compare Submodule Controlling and Monitoring the Counter-Compare SubmoduleCounter-Compare Submodule Registers Register Name Address OffsetCount Mode Timing Waveforms Counter-Compare Submodule Key Signals∙ Shadow Mode ∙ Immediate Load ModeCTR=CMPA CTR=CMPBCTR = Cmpb Action-Qualifier AQ Submodule Purpose of the Action-Qualifier SubmoduleAction-Qualifier Submodule Registers Action-Qualifier Submodule Possible Input Events ∙ Set High∙ Clear Low ∙ ToggleTB Counter equals Actions Action-Qualifier Event Priority for Up-Down-Count Mode Action-Qualifier Event Priority for Up-Count Mode10. Action-Qualifier Event Priority for Down-Count Mode Action-Qualifier Event PriorityWaveforms for Common Configurations Use up-down-count mode to generate a symmetric PWMUse up-down-count mode to generate an asymmetric PWM When using up-count mode to generate an asymmetric PWM20. Up-Down-Count Mode Symmetrical Waveform Example 2-2. Code Sample for Figure TbctrValue EPWMxA EPWMxB Example 2-3. Code Sample for Figure Tbclk = SysclkoutExample 2-4. Code Sample for Figure EdgePosAExample 2-5. Code Sample for Figure Example 2-6. Code Sample for Figure TbctrExample 2-7. Code Sample for Figure EPWMxA EPWMxBDead-Band Generator DB Submodule Purpose of the Dead-Band SubmoduleControlling and Monitoring the Dead-Band Submodule 12. Dead-Band Generator Submodule Registers∙ Output Mode Control Operational Highlights for the Dead-Band Submodule∙ Input Source Selection ∙ Polarity ControlMode Description 13. Classical Dead-Band Operating Modes29. Dead-Band Waveforms for Typical Cases 0% Duty 100% Dead-Band Delay in μS FED = Dbfed × Ttbclk RED = Dbred × TtbclkPWM-Chopper PC Submodule Purpose of the PWM-Chopper SubmoduleControlling the PWM-Chopper Submodule Operational Highlights for the PWM-Chopper SubmoduleWaveforms 31. PWM-Chopper Submodule Operational DetailsOne-Shot Pulse 16. Possible Pulse Width Values for Sysclkout = 100 MHzOSHTWTHz Duty Cycle Control PeriodTrip-Zone TZ Submodule Purpose of the Trip-Zone SubmoduleControlling and Monitoring the Trip-Zone Submodule Operational Highlights for the Trip-Zone Submodule17. Trip-Zone Submodule Registers ∙ Cycle-by-Cycle CBCExample 2-8. Trip-Zone Configurations 18. Possible Actions On a Trip EventScenario a Scenario B36. Trip-Zone Submodule Mode Control Logic Generating Trip Event InterruptsEvent-Trigger ET Submodule 37. Trip-Zone Submodule Interrupt LogicOperational Overview of the Event-Trigger Submodule 19. Event-Trigger Submodule Registers CTR=CMPB CTRD=CMPB41. Event-Trigger Interrupt Generator 42. Event-Trigger Soca Pulse Generator Submit Documentation Feedback Applications to Power Topologies Controlling Multiple Buck Converters With IndependentKey Configuration Capabilities Overview of Multiple ModulesCTR=0 EPWM1B CTR=CMPB Control of Four Buck Stages. Here FPWM1≠ FPWM2≠ FPWM3≠ FPWM4 Buck Waveforms for -3Note Only three bucks shown here Example 3-1. Configuration for Example in Figure 500Controlling Multiple Buck Converters With Same Frequencies Control of Four Buck Stages. Note FPWM2 = N x FPWM1Buck Waveforms for -5Note FPWM2 = FPWM1 Example 3-2. Code Snippet for Configuration in Figure Controlling Multiple Half H-Bridge HHB Converters Control of Two Half-H Bridge Stages FPWM2 = N x FPWM1Half-H Bridge Waveforms for -7Note Here FPWM2 = FPWM1 Controlling Dual 3-Phase Inverters for Motors ACI and Pmsm Example 3-3. Code Snippet for Configuration in FigureEPWM1A 10 -Phase Inverter Waveforms for -9Only One Inverter Shown Example 3-4. Code Snippet for Configuration in Figure 11. Configuring Two PWM Modules for Phase Control Controlling a 3-Phase Interleaved DC/DC Converter Controlling a 3-Phase Interleaved DC/DC Converter13. Control of a 3-Phase Interleaved DC/DC Converter 14 -Phase Interleaved DC/DC Converter Waveforms for Figure Example 3-5. Code Snippet for Configuration in Figure 15. Controlling a Full-H Bridge Stage FPWM2 = FPWM1 16. ZVS Full-H Bridge Waveforms Example 3-6. Code Snippet for Configuration in Figure Submit Documentation Feedback Proper Interrupt Initialization Procedure PWM-Chopper Submodule Control RegisterTrip-Zone Submodule Control and Status Registers Time-Base Phase Register Tbphs Field Descriptions Time-Base Submodule RegistersTime-Base Period Register Tbprd Field Descriptions Time-Base Counter Register Tbctr Field DescriptionsTime-Base Control Register Tbctl Field Descriptions Bit Field Value DescriptionSoftware Forced Synchronization Pulse Counter-Compare Submodule Registers Time-Base Status Register Tbsts Field DescriptionsBit Field Counter-Compare a Register Cmpa Field Descriptions Counter-Compare B Register Cmpb Field DescriptionsBits Name Description Action-Qualifier Submodule Registers Counter-Compare Control Register Cmpctl Field DescriptionsCBD CBU CAD CAU PRD ZRO Bits NameCBD 10. Action-Qualifier Output B Control Register Aqctlb Rldcsf Otsfb Actsfb Otsfa Actsfa RldcsfCsfb Csfa Dead-Band Submodule Registers CsfbInmode Polsel Outmode Inmode PWM-Chopper Submodule Control Register 16. PWM-Chopper Control Register Pcctl Bit DescriptionsName Value Description ReservedTrip-Zone Submodule Control and Status Registers PWM-Chopper Control Register Pcctl Bit DescriptionsChpduty OSHT6 OSHT5 OSHT4 OSHT3 OSHT2 OSHT1 CBC6 CBC5 CBC4 CBC3 CBC2 CBC1OSHT6 CBC618. Trip-Zone Control Register Tzctl Field Descriptions TZB TZATZB OST CBC20. Trip-Zone Flag Register Tzflg Field Descriptions OST CBC INTEvent-Trigger Submodule Registers 21. Trip-Zone Clear Register Tzclr Field Descriptions22. Trip-Zone Force Register Tzfrc Field Descriptions 23. Event-Trigger Selection Register Etsel 24. Event-Trigger Prescale Register Etps Field Descriptions Name Description24. Event-Trigger Prescale Register Etps Field Descriptions Socb Soca25. Event-Trigger Flag Register Etflg Field Descriptions 26. Event-Trigger Clear Register Etclr Field DescriptionsSocb Proper Interrupt Initialization Procedure 27. Event-Trigger Force Register Etfrc Field Descriptions116 Table A-1. Changes for Revision D Location Modifications, Additions, and DeletionsAppendix a Important Notice
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