Texas Instruments 28xxx, TMS320x28xx manual List of Figures

Page 5

List of Figures

1-1

Multiple ePWM Modules

15

1-2

Submodules and Signal Connections for an ePWM Module

16

1-3

ePWM Submodules and Critical Internal Signal Interconnects

17

2-1

Time-Base Submodule Block Diagram

23

2-2

Time-Base Submodule Signals and Registers

24

2-3

Time-Base Frequency and Period

26

2-4

Time-Base Counter Synchronization Scheme 1

27

2-5

Time-Base Counter Synchronization Scheme 2

28

2-6

Time-Base Counter Synchronization Scheme 3

29

2-7

Time-BaseUp-Count Mode Waveforms

30

2-8

Time-BaseDown-Count Mode Waveforms

31

2-9

Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count Down On Synchronization Event

31

2-10

Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count Up On Synchronization Event

32

2-11

Counter-Compare Submodule

32

2-12

Detailed View of the Counter-Compare Submodule

33

2-13

Counter-Compare Event Waveforms in Up-Count Mode

35

2-14

Counter-Compare Events in Down-Count Mode

35

2-15

Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count Down On

 

 

 

Synchronization Event

36

2-16

Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count Up On Synchronization

 

 

Event

36

2-17

Action-Qualifier Submodule

37

2-18

Action-Qualifier Submodule Inputs and Outputs

38

2-19

Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs

39

2-20

Up-Down-Count Mode Symmetrical Waveform

42

2-21

Up, Single Edge Asymmetric Waveform, With Independent Modulation on EPWMxA and

 

 

 

EPWMxB—Active High

43

2-22

Up, Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and

 

 

 

EPWMxB—Active Low

44

2-23

Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA

45

2-24

Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and

 

 

EPWMxB — Active Low

47

2-25

Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and

 

 

EPWMxB — Complementary

48

2-26

Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation on EPWMxA—Active

 

 

Low

49

2-27

Dead_Band Submodule

50

2-28

Configuration Options for the Dead-Band Submodule

51

2-29

Dead-Band Waveforms for Typical Cases (0% < Duty < 100%)

53

2-30

PWM-Chopper Submodule

55

2-31

PWM-Chopper Submodule Operational Details

56

2-32

Simple PWM-Chopper Submodule Waveforms Showing Chopping Action Only

56

2-33

PWM-Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses

57

2-34

PWM-Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining

 

 

Pulses

58

2-35

Trip-Zone Submodule

59

2-36

Trip-Zone Submodule Mode Control Logic

62

2-37

Trip-Zone Submodule Interrupt Logic

63

2-38

Event-Trigger Submodule

63

2-39

Event-Trigger Submodule Inter-Connectivity of ADC Start of Conversion and Interrupt Signals

64

2-40

Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs

65

2-41

Event-Trigger Interrupt Generator

66

2-42

Event-Trigger SOCA Pulse Generator

67

SPRU791D–November 2004–Revised October 2007

List of Figures

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Contents Reference Guide Submit Documentation Feedback Contents Controlling a 3-Phase Interleaved DC/DC Converter List of Figures Event-Trigger Socb Pulse Generator Simplified ePWM Module List of Tables Submit Documentation Feedback Data Manuals Related Documentation From Texas InstrumentsCPU Users Guides Peripheral GuidesApplication Reports Tools GuidesTMS320C28x, C28x are trademarks of Texas Instruments TrademarksSubmit Documentation Feedback Introduction Submodule Overview IntroductionMultiple ePWM Modules ∙ Trip-zone signals TZ1 to TZ6 ∙ PWM output signals EPWMxA and EPWMxB∙ ADC start-of-conversion signals EPWMxSOCA and EPWMxSOCB ∙ Peripheral BusRegister Mapping EPWM Submodules and Critical Internal Signal InterconnectsDescription Offset Size NameTime-Base Submodule Registers Counter-Compare Submodule RegistersEPWM Submodules Overview Submodule Configuration ParametersSubmodule Configuration Parameter or Option Tbup Example 2-1. Constant Definitions Used in the Code ExamplesChpenable Purpose of the Time-Base Submodule Time-Base TB SubmoduleRegister Controlling and Monitoring the Time-base SubmoduleTime-Base Submodule Registers ∙ Up-Down-Count Mode Key Time-Base Signals∙ Up-Count Mode ∙ Down-Count Mode∙ Time-Base Period Immediate Load Mode ∙ Time-Base Period Shadow ModeTime-Base Period Shadow Register ∙ Active RegisterTime-Base Counter Synchronization Scheme Time-Base Counter SynchronizationEPWM11SYNCO EPWM11SYNCI∙ Software Forced Synchronization Pulse ∙ EPWMxSYNCI Synchronization Input PulseTime-base Counter Modes and Timing Waveforms Phase Locking the Time-Base Clocks of Multiple ePWM ModulesTime-Base Down-Count Mode Waveforms 11. Counter-Compare Submodule Counter-Compare CC SubmoduleControlling and Monitoring the Counter-Compare Submodule Purpose of the Counter-Compare SubmoduleCounter-Compare Submodule Registers Register Name Address OffsetCounter-Compare Submodule Key Signals Count Mode Timing Waveforms∙ Shadow Mode ∙ Immediate Load ModeCTR=CMPB CTR=CMPACTR = Cmpb Action-Qualifier Submodule Registers Action-Qualifier AQ SubmodulePurpose of the Action-Qualifier Submodule ∙ Set High Action-Qualifier Submodule Possible Input Events∙ Clear Low ∙ ToggleTB Counter equals Actions Action-Qualifier Event Priority for Up-Count Mode Action-Qualifier Event Priority for Up-Down-Count Mode10. Action-Qualifier Event Priority for Down-Count Mode Action-Qualifier Event PriorityUse up-down-count mode to generate a symmetric PWM Waveforms for Common ConfigurationsUse up-down-count mode to generate an asymmetric PWM When using up-count mode to generate an asymmetric PWM20. Up-Down-Count Mode Symmetrical Waveform Tbctr Example 2-2. Code Sample for FigureValue EPWMxA EPWMxB Tbclk = Sysclkout Example 2-3. Code Sample for FigureEdgePosA Example 2-4. Code Sample for FigureExample 2-5. Code Sample for Figure Tbctr Example 2-6. Code Sample for FigureEPWMxA EPWMxB Example 2-7. Code Sample for FigurePurpose of the Dead-Band Submodule Dead-Band Generator DB SubmoduleControlling and Monitoring the Dead-Band Submodule 12. Dead-Band Generator Submodule RegistersOperational Highlights for the Dead-Band Submodule ∙ Output Mode Control∙ Input Source Selection ∙ Polarity Control13. Classical Dead-Band Operating Modes Mode Description29. Dead-Band Waveforms for Typical Cases 0% Duty 100% FED = Dbfed × Ttbclk RED = Dbred × Ttbclk Dead-Band Delay in μSPurpose of the PWM-Chopper Submodule PWM-Chopper PC SubmoduleControlling the PWM-Chopper Submodule Operational Highlights for the PWM-Chopper Submodule31. PWM-Chopper Submodule Operational Details WaveformsOSHTWTHz One-Shot Pulse16. Possible Pulse Width Values for Sysclkout = 100 MHz Period Duty Cycle ControlPurpose of the Trip-Zone Submodule Trip-Zone TZ SubmoduleOperational Highlights for the Trip-Zone Submodule Controlling and Monitoring the Trip-Zone Submodule17. Trip-Zone Submodule Registers ∙ Cycle-by-Cycle CBC18. Possible Actions On a Trip Event Example 2-8. Trip-Zone ConfigurationsScenario a Scenario BGenerating Trip Event Interrupts 36. Trip-Zone Submodule Mode Control Logic37. Trip-Zone Submodule Interrupt Logic Event-Trigger ET SubmoduleOperational Overview of the Event-Trigger Submodule CTR=CMPB CTRD=CMPB 19. Event-Trigger Submodule Registers41. Event-Trigger Interrupt Generator 42. Event-Trigger Soca Pulse Generator Submit Documentation Feedback Controlling Multiple Buck Converters With Independent Applications to Power TopologiesOverview of Multiple Modules Key Configuration CapabilitiesCTR=0 EPWM1B CTR=CMPB Control of Four Buck Stages. Here FPWM1≠ FPWM2≠ FPWM3≠ FPWM4 Buck Waveforms for -3Note Only three bucks shown here 500 Example 3-1. Configuration for Example in FigureControl of Four Buck Stages. Note FPWM2 = N x FPWM1 Controlling Multiple Buck Converters With Same FrequenciesBuck Waveforms for -5Note FPWM2 = FPWM1 Example 3-2. Code Snippet for Configuration in Figure Control of Two Half-H Bridge Stages FPWM2 = N x FPWM1 Controlling Multiple Half H-Bridge HHB ConvertersHalf-H Bridge Waveforms for -7Note Here FPWM2 = FPWM1 Example 3-3. Code Snippet for Configuration in Figure Controlling Dual 3-Phase Inverters for Motors ACI and PmsmEPWM1A 10 -Phase Inverter Waveforms for -9Only One Inverter Shown Example 3-4. Code Snippet for Configuration in Figure 11. Configuring Two PWM Modules for Phase Control Controlling a 3-Phase Interleaved DC/DC Converter Controlling a 3-Phase Interleaved DC/DC Converter13. Control of a 3-Phase Interleaved DC/DC Converter 14 -Phase Interleaved DC/DC Converter Waveforms for Figure Example 3-5. Code Snippet for Configuration in Figure 15. Controlling a Full-H Bridge Stage FPWM2 = FPWM1 16. ZVS Full-H Bridge Waveforms Example 3-6. Code Snippet for Configuration in Figure Submit Documentation Feedback Trip-Zone Submodule Control and Status Registers Proper Interrupt Initialization ProcedurePWM-Chopper Submodule Control Register Time-Base Submodule Registers Time-Base Phase Register Tbphs Field DescriptionsTime-Base Period Register Tbprd Field Descriptions Time-Base Counter Register Tbctr Field DescriptionsBit Field Value Description Time-Base Control Register Tbctl Field DescriptionsSoftware Forced Synchronization Pulse Bit Field Counter-Compare Submodule RegistersTime-Base Status Register Tbsts Field Descriptions Bits Name Description Counter-Compare a Register Cmpa Field DescriptionsCounter-Compare B Register Cmpb Field Descriptions Counter-Compare Control Register Cmpctl Field Descriptions Action-Qualifier Submodule RegistersCBD CBD CBU CAD CAU PRD ZROBits Name 10. Action-Qualifier Output B Control Register Aqctlb Csfb Csfa Rldcsf Otsfb Actsfb Otsfa ActsfaRldcsf Inmode Polsel Outmode Dead-Band Submodule RegistersCsfb Inmode 16. PWM-Chopper Control Register Pcctl Bit Descriptions PWM-Chopper Submodule Control RegisterName Value Description ReservedChpduty Trip-Zone Submodule Control and Status RegistersPWM-Chopper Control Register Pcctl Bit Descriptions CBC6 CBC5 CBC4 CBC3 CBC2 CBC1 OSHT6 OSHT5 OSHT4 OSHT3 OSHT2 OSHT1OSHT6 CBC6TZB TZA 18. Trip-Zone Control Register Tzctl Field DescriptionsTZB OST CBCOST CBC INT 20. Trip-Zone Flag Register Tzflg Field Descriptions22. Trip-Zone Force Register Tzfrc Field Descriptions Event-Trigger Submodule Registers21. Trip-Zone Clear Register Tzclr Field Descriptions 23. Event-Trigger Selection Register Etsel Name Description 24. Event-Trigger Prescale Register Etps Field DescriptionsSocb Soca 24. Event-Trigger Prescale Register Etps Field DescriptionsSocb 25. Event-Trigger Flag Register Etflg Field Descriptions26. Event-Trigger Clear Register Etclr Field Descriptions 27. Event-Trigger Force Register Etfrc Field Descriptions Proper Interrupt Initialization Procedure116 Location Modifications, Additions, and Deletions Table A-1. Changes for Revision DAppendix a Important Notice
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