Texas Instruments TMS320x28xx, 28xxx Operational Highlights for the Counter-Compare Submodule

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Counter-Compare (CC) Submodule

The key signals associated with the counter-compare submodule are described in Table 2-5.

Table 2-5. Counter-Compare Submodule Key Signals

Signal

Description of Event

Registers Compared

CTR = CMPA

Time-base counter equal to the active counter-compare A value

TBCTR = CMPA

CTR = CMPB

Time-base counter equal to the active counter-compare B value

TBCTR = CMPB

CTR = PRD

Time-base counter equal to the active period.

TBCTR = TBPRD

 

Used to load active counter-compare A and B registers from the

 

 

shadow register

 

CTR = ZERO

Time-base counter equal to zero.

TBCTR = 0x0000

 

Used to load active counter-compare A and B registers from the

 

 

shadow register

 

2.3.3 Operational Highlights for the Counter-Compare Submodule

The counter-compare submodule is responsible for generating two independent compare events based on two compare registers:

1.CTR = CMPA: Time-base counter equal to counter-compare A register (TBCTR = CMPA).

2.CTR = CMPB: Time-base counter equal to counter-compare B register (TBCTR = CMPB).

For up-count or down-count mode, each event occurs only once per cycle. For up-down-count mode each event occurs twice per cycle if the compare value is between 0x0000-TBPRD and once per cycle if the compare value is equal to 0x0000 or equal to TBPRD. These events are fed into the action-qualifier submodule where they are qualified by the counter direction and converted into actions if enabled. Refer to Section 2.4.1 for more details.

The counter-compare registers CMPA and CMPB each have an associated shadow register. Shadowing provides a way to keep updates to the registers synchronized with the hardware. When shadowing is used, updates to the active registers only occurs at strategic points. This prevents corruption or spurious operation due to the register being asynchronously modified by software. The memory address of the active register and the shadow register is identical. Which register is written to or read from is determined by the CMPCTL[SHDWAMODE] and CMPCTL[SHDWBMODE] bits. These bits enable and disable the CMPA shadow register and CMPB shadow register respectively. The behavior of the two load modes is described below:

∙Shadow Mode:

The shadow mode for the CMPA is enabled by clearing the CMPCTL[SHDWAMODE] bit and the shadow register for CMPB is enabled by clearing the CMPCTL[SHDWBMODE] bit. Shadow mode is enabled by default for both CMPA and CMPB.

If the shadow register is enabled then the content of the shadow register is transferred to the active register on one of the following events:

–CTR = PRD: Time-base counter equal to the period (TBCTR = TBPRD).

–CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)

–Both CTR = PRD and CTR = Zero

Which of these three events is specified by the CMPCTL[LOADAMODE] and CMPCTL[LOADBMODE] register bits. Only the active register contents are used by the counter-compare submodule to generate events to be sent to the action-qualifier.

∙Immediate Load Mode:

If immediate load mode is selected (i.e., TBCTL[SHADWAMODE] = 1 or TBCTL[SHADWBMODE] = 1), then a read from or a write to the register will go directly to the active register.

2.3.4Count Mode Timing Waveforms

The counter-compare module can generate compare events in all three count modes:

∙Up-count mode: used to generate an asymmetrical PWM waveform.

∙Down-count mode: used to generate an asymmetrical PWM waveform.

34

ePWM Submodules

SPRU791D–November 2004–Revised October 2007

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Contents Reference Guide Submit Documentation Feedback Contents Controlling a 3-Phase Interleaved DC/DC Converter List of Figures Event-Trigger Socb Pulse Generator Simplified ePWM Module List of Tables Submit Documentation Feedback CPU Users Guides Related Documentation From Texas InstrumentsData Manuals Peripheral GuidesTools Guides Application ReportsTrademarks TMS320C28x, C28x are trademarks of Texas InstrumentsSubmit Documentation Feedback Introduction Introduction Submodule OverviewMultiple ePWM Modules ∙ ADC start-of-conversion signals EPWMxSOCA and EPWMxSOCB ∙ PWM output signals EPWMxA and EPWMxB∙ Trip-zone signals TZ1 to TZ6 ∙ Peripheral BusEPWM Submodules and Critical Internal Signal Interconnects Register MappingTime-Base Submodule Registers Offset Size NameDescription Counter-Compare Submodule RegistersEPWM Submodules Submodule Configuration Parameter or Option Submodule Configuration ParametersOverview Example 2-1. Constant Definitions Used in the Code Examples TbupChpenable Time-Base TB Submodule Purpose of the Time-Base SubmoduleTime-Base Submodule Registers Controlling and Monitoring the Time-base SubmoduleRegister ∙ Up-Count Mode Key Time-Base Signals∙ Up-Down-Count Mode ∙ Down-Count ModeTime-Base Period Shadow Register ∙ Time-Base Period Shadow Mode∙ Time-Base Period Immediate Load Mode ∙ Active RegisterTime-Base Counter Synchronization Time-Base Counter Synchronization SchemeEPWM11SYNCI EPWM11SYNCO∙ EPWMxSYNCI Synchronization Input Pulse ∙ Software Forced Synchronization PulsePhase Locking the Time-Base Clocks of Multiple ePWM Modules Time-base Counter Modes and Timing WaveformsTime-Base Down-Count Mode Waveforms Counter-Compare CC Submodule 11. Counter-Compare SubmoduleCounter-Compare Submodule Registers Purpose of the Counter-Compare SubmoduleControlling and Monitoring the Counter-Compare Submodule Register Name Address Offset∙ Shadow Mode Count Mode Timing WaveformsCounter-Compare Submodule Key Signals ∙ Immediate Load ModeCTR=CMPA CTR=CMPBCTR = Cmpb Purpose of the Action-Qualifier Submodule Action-Qualifier AQ SubmoduleAction-Qualifier Submodule Registers ∙ Clear Low Action-Qualifier Submodule Possible Input Events∙ Set High ∙ ToggleTB Counter equals Actions 10. Action-Qualifier Event Priority for Down-Count Mode Action-Qualifier Event Priority for Up-Down-Count ModeAction-Qualifier Event Priority for Up-Count Mode Action-Qualifier Event PriorityUse up-down-count mode to generate an asymmetric PWM Waveforms for Common ConfigurationsUse up-down-count mode to generate a symmetric PWM When using up-count mode to generate an asymmetric PWM20. Up-Down-Count Mode Symmetrical Waveform Example 2-2. Code Sample for Figure TbctrValue EPWMxA EPWMxB Example 2-3. Code Sample for Figure Tbclk = SysclkoutExample 2-4. Code Sample for Figure EdgePosAExample 2-5. Code Sample for Figure Example 2-6. Code Sample for Figure TbctrExample 2-7. Code Sample for Figure EPWMxA EPWMxBControlling and Monitoring the Dead-Band Submodule Dead-Band Generator DB SubmodulePurpose of the Dead-Band Submodule 12. Dead-Band Generator Submodule Registers∙ Input Source Selection ∙ Output Mode ControlOperational Highlights for the Dead-Band Submodule ∙ Polarity ControlMode Description 13. Classical Dead-Band Operating Modes29. Dead-Band Waveforms for Typical Cases 0% Duty 100% Dead-Band Delay in μS FED = Dbfed × Ttbclk RED = Dbred × TtbclkControlling the PWM-Chopper Submodule PWM-Chopper PC SubmodulePurpose of the PWM-Chopper Submodule Operational Highlights for the PWM-Chopper SubmoduleWaveforms 31. PWM-Chopper Submodule Operational Details16. Possible Pulse Width Values for Sysclkout = 100 MHz One-Shot PulseOSHTWTHz Duty Cycle Control PeriodTrip-Zone TZ Submodule Purpose of the Trip-Zone Submodule17. Trip-Zone Submodule Registers Controlling and Monitoring the Trip-Zone SubmoduleOperational Highlights for the Trip-Zone Submodule ∙ Cycle-by-Cycle CBCScenario a Example 2-8. Trip-Zone Configurations18. Possible Actions On a Trip Event Scenario B36. Trip-Zone Submodule Mode Control Logic Generating Trip Event InterruptsEvent-Trigger ET Submodule 37. Trip-Zone Submodule Interrupt LogicOperational Overview of the Event-Trigger Submodule 19. Event-Trigger Submodule Registers CTR=CMPB CTRD=CMPB41. Event-Trigger Interrupt Generator 42. Event-Trigger Soca Pulse Generator Submit Documentation Feedback Applications to Power Topologies Controlling Multiple Buck Converters With IndependentKey Configuration Capabilities Overview of Multiple ModulesCTR=0 EPWM1B CTR=CMPB Control of Four Buck Stages. Here FPWM1≠ FPWM2≠ FPWM3≠ FPWM4 Buck Waveforms for -3Note Only three bucks shown here Example 3-1. Configuration for Example in Figure 500Controlling Multiple Buck Converters With Same Frequencies Control of Four Buck Stages. Note FPWM2 = N x FPWM1Buck Waveforms for -5Note FPWM2 = FPWM1 Example 3-2. Code Snippet for Configuration in Figure Controlling Multiple Half H-Bridge HHB Converters Control of Two Half-H Bridge Stages FPWM2 = N x FPWM1Half-H Bridge Waveforms for -7Note Here FPWM2 = FPWM1 Controlling Dual 3-Phase Inverters for Motors ACI and Pmsm Example 3-3. Code Snippet for Configuration in FigureEPWM1A 10 -Phase Inverter Waveforms for -9Only One Inverter Shown Example 3-4. Code Snippet for Configuration in Figure 11. Configuring Two PWM Modules for Phase Control Controlling a 3-Phase Interleaved DC/DC Converter Controlling a 3-Phase Interleaved DC/DC Converter13. Control of a 3-Phase Interleaved DC/DC Converter 14 -Phase Interleaved DC/DC Converter Waveforms for Figure Example 3-5. Code Snippet for Configuration in Figure 15. Controlling a Full-H Bridge Stage FPWM2 = FPWM1 16. ZVS Full-H Bridge Waveforms Example 3-6. Code Snippet for Configuration in Figure Submit Documentation Feedback PWM-Chopper Submodule Control Register Proper Interrupt Initialization ProcedureTrip-Zone Submodule Control and Status Registers Time-Base Period Register Tbprd Field Descriptions Time-Base Phase Register Tbphs Field DescriptionsTime-Base Submodule Registers Time-Base Counter Register Tbctr Field DescriptionsTime-Base Control Register Tbctl Field Descriptions Bit Field Value DescriptionSoftware Forced Synchronization Pulse Time-Base Status Register Tbsts Field Descriptions Counter-Compare Submodule RegistersBit Field Counter-Compare B Register Cmpb Field Descriptions Counter-Compare a Register Cmpa Field DescriptionsBits Name Description Action-Qualifier Submodule Registers Counter-Compare Control Register Cmpctl Field DescriptionsBits Name CBD CBU CAD CAU PRD ZROCBD 10. Action-Qualifier Output B Control Register Aqctlb Rldcsf Rldcsf Otsfb Actsfb Otsfa ActsfaCsfb Csfa Csfb Dead-Band Submodule RegistersInmode Polsel Outmode Inmode Name Value Description PWM-Chopper Submodule Control Register16. PWM-Chopper Control Register Pcctl Bit Descriptions ReservedPWM-Chopper Control Register Pcctl Bit Descriptions Trip-Zone Submodule Control and Status RegistersChpduty OSHT6 OSHT6 OSHT5 OSHT4 OSHT3 OSHT2 OSHT1CBC6 CBC5 CBC4 CBC3 CBC2 CBC1 CBC6TZB 18. Trip-Zone Control Register Tzctl Field DescriptionsTZB TZA OST CBC20. Trip-Zone Flag Register Tzflg Field Descriptions OST CBC INT21. Trip-Zone Clear Register Tzclr Field Descriptions Event-Trigger Submodule Registers22. Trip-Zone Force Register Tzfrc Field Descriptions 23. Event-Trigger Selection Register Etsel 24. Event-Trigger Prescale Register Etps Field Descriptions Name Description24. Event-Trigger Prescale Register Etps Field Descriptions Socb Soca26. Event-Trigger Clear Register Etclr Field Descriptions 25. Event-Trigger Flag Register Etflg Field DescriptionsSocb Proper Interrupt Initialization Procedure 27. Event-Trigger Force Register Etfrc Field Descriptions116 Table A-1. Changes for Revision D Location Modifications, Additions, and DeletionsAppendix a Important Notice
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