Texas Instruments 28xxx Purpose of the Counter-Compare Submodule, Register Name Address Offset

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Counter-Compare (CC) Submodule

2.3.1 Purpose of the Counter-Compare Submodule

The counter-compare submodule takes as input the time-base counter value. This value is continuously compared to the counter-compare A (CMPA) and counter-compare B (CMPB) registers. When the time-base counter is equal to one of the compare registers, the counter-compare unit generates an appropriate event.

The counter-compare:

∙Generates events based on programmable time stamps using the CMPA and CMPB registers

–CTR = CMPA: Time-base counter equals counter-compare A register (TBCTR = CMPA).

–CTR = CMPB: Time-base counter equals counter-compare B register (TBCTR = CMPB)

∙Controls the PWM duty cycle if the action-qualifier submodule is configured appropriately

∙Shadows new compare values to prevent corruption or glitches during the active PWM cycle

2.3.2Controlling and Monitoring the Counter-Compare Submodule

The counter-compare submodule operation is controlled and monitored by the registers shown in Table 2-4:

Table 2-4. Counter-Compare Submodule Registers

Register Name

Address Offset

Shadowed

Description

CMPCTL

0x0007

No

Counter-Compare Control Register.

CMPAHR

0x0008

Yes

HRPWM Counter-Compare A Extension Register (1)

CMPA

0x0009

Yes

Counter-Compare A Register

CMPB

0x000A

Yes

Counter-Compare B Register

(1)This register is available only on ePWM modules with the high-resolution extension (HRPWM). On ePWM modules that do not include the HRPWM this location is reserved. This register is described in the TMS320x28xx, 28xxx High-Resolution Pulse Width Modulator (HRPWM) Reference Guide (SPRU924). Refer to the device specific data manual to determine which ePWM instances include this feature.

Figure 2-12. Detailed View of the Counter-Compare Submodule

 

Time

TBCTR[15:0]

16

 

Base

 

 

 

(TB)

 

 

 

Module

 

16

 

 

CMPA[15:0]

 

 

 

CTR￿=￿PRD

Shadow

CMPA

 

CTR￿=0

load

Compare￿A￿Active￿Reg.

 

CMPA

 

 

 

 

 

 

Compare￿A￿Shadow￿Reg.

CMPCTL[LOADAMODE]

TBCTR[15:0]

16

 

 

 

 

 

CMPB[15:0]

16

 

 

 

 

 

 

 

Shadow

 

 

 

 

 

 

 

 

 

 

 

 

 

CTR￿=￿PRD

 

 

 

 

CMPB

 

 

 

 

load

 

 

 

 

 

 

 

Compare￿B￿Active￿Reg.

 

CTR￿=￿0

 

 

 

 

 

 

 

 

 

 

 

CMPB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Compare￿B￿Shadow￿Reg.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CTR￿=￿CMPA

 

 

 

 

 

 

 

Digital

 

comparator￿A

 

 

CMPCTL

 

[SHDWAFULL]

Action

 

 

 

 

 

 

CMPCTL

Qualifier

 

(AQ)

[SHDWAMODE]

Module

 

 

 

 

 

 

 

 

 

 

CTR￿=￿CMPB

Digital comparator￿B

CMPCTL[SHDWBFULL]

CMPCTL[SHDWBMODE]

CMPCTL[LOADBMODE]

SPRU791D–November 2004–Revised October 2007

ePWM Submodules

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Contents Reference Guide Submit Documentation Feedback Contents Controlling a 3-Phase Interleaved DC/DC Converter List of Figures Event-Trigger Socb Pulse Generator Simplified ePWM Module List of Tables Submit Documentation Feedback Data Manuals Related Documentation From Texas InstrumentsCPU Users Guides Peripheral GuidesApplication Reports Tools GuidesTMS320C28x, C28x are trademarks of Texas Instruments TrademarksSubmit Documentation Feedback Introduction Submodule Overview IntroductionMultiple ePWM Modules ∙ Trip-zone signals TZ1 to TZ6 ∙ PWM output signals EPWMxA and EPWMxB∙ ADC start-of-conversion signals EPWMxSOCA and EPWMxSOCB ∙ Peripheral BusRegister Mapping EPWM Submodules and Critical Internal Signal InterconnectsDescription Offset Size NameTime-Base Submodule Registers Counter-Compare Submodule RegistersEPWM Submodules Submodule Configuration Parameters Submodule Configuration Parameter or OptionOverview Tbup Example 2-1. Constant Definitions Used in the Code ExamplesChpenable Purpose of the Time-Base Submodule Time-Base TB SubmoduleControlling and Monitoring the Time-base Submodule Time-Base Submodule RegistersRegister ∙ Up-Down-Count Mode Key Time-Base Signals∙ Up-Count Mode ∙ Down-Count Mode∙ Time-Base Period Immediate Load Mode ∙ Time-Base Period Shadow ModeTime-Base Period Shadow Register ∙ Active RegisterTime-Base Counter Synchronization Scheme Time-Base Counter SynchronizationEPWM11SYNCO EPWM11SYNCI∙ Software Forced Synchronization Pulse ∙ EPWMxSYNCI Synchronization Input PulseTime-base Counter Modes and Timing Waveforms Phase Locking the Time-Base Clocks of Multiple ePWM ModulesTime-Base Down-Count Mode Waveforms 11. Counter-Compare Submodule Counter-Compare CC SubmoduleControlling and Monitoring the Counter-Compare Submodule Purpose of the Counter-Compare SubmoduleCounter-Compare Submodule Registers Register Name Address OffsetCounter-Compare Submodule Key Signals Count Mode Timing Waveforms∙ Shadow Mode ∙ Immediate Load ModeCTR=CMPB CTR=CMPACTR = Cmpb Action-Qualifier AQ Submodule Purpose of the Action-Qualifier SubmoduleAction-Qualifier Submodule Registers ∙ Set High Action-Qualifier Submodule Possible Input Events∙ Clear Low ∙ ToggleTB Counter equals Actions Action-Qualifier Event Priority for Up-Count Mode Action-Qualifier Event Priority for Up-Down-Count Mode10. Action-Qualifier Event Priority for Down-Count Mode Action-Qualifier Event PriorityUse up-down-count mode to generate a symmetric PWM Waveforms for Common ConfigurationsUse up-down-count mode to generate an asymmetric PWM When using up-count mode to generate an asymmetric PWM20. Up-Down-Count Mode Symmetrical Waveform Tbctr Example 2-2. Code Sample for FigureValue EPWMxA EPWMxB Tbclk = Sysclkout Example 2-3. Code Sample for FigureEdgePosA Example 2-4. Code Sample for FigureExample 2-5. Code Sample for Figure Tbctr Example 2-6. Code Sample for FigureEPWMxA EPWMxB Example 2-7. Code Sample for FigurePurpose of the Dead-Band Submodule Dead-Band Generator DB SubmoduleControlling and Monitoring the Dead-Band Submodule 12. Dead-Band Generator Submodule RegistersOperational Highlights for the Dead-Band Submodule ∙ Output Mode Control∙ Input Source Selection ∙ Polarity Control13. Classical Dead-Band Operating Modes Mode Description29. Dead-Band Waveforms for Typical Cases 0% Duty 100% FED = Dbfed × Ttbclk RED = Dbred × Ttbclk Dead-Band Delay in μSPurpose of the PWM-Chopper Submodule PWM-Chopper PC SubmoduleControlling the PWM-Chopper Submodule Operational Highlights for the PWM-Chopper Submodule31. PWM-Chopper Submodule Operational Details WaveformsOne-Shot Pulse 16. Possible Pulse Width Values for Sysclkout = 100 MHzOSHTWTHz Period Duty Cycle ControlPurpose of the Trip-Zone Submodule Trip-Zone TZ SubmoduleOperational Highlights for the Trip-Zone Submodule Controlling and Monitoring the Trip-Zone Submodule17. Trip-Zone Submodule Registers ∙ Cycle-by-Cycle CBC18. Possible Actions On a Trip Event Example 2-8. Trip-Zone ConfigurationsScenario a Scenario BGenerating Trip Event Interrupts 36. Trip-Zone Submodule Mode Control Logic37. Trip-Zone Submodule Interrupt Logic Event-Trigger ET SubmoduleOperational Overview of the Event-Trigger Submodule CTR=CMPB CTRD=CMPB 19. Event-Trigger Submodule Registers41. Event-Trigger Interrupt Generator 42. Event-Trigger Soca Pulse Generator Submit Documentation Feedback Controlling Multiple Buck Converters With Independent Applications to Power TopologiesOverview of Multiple Modules Key Configuration CapabilitiesCTR=0 EPWM1B CTR=CMPB Control of Four Buck Stages. Here FPWM1≠ FPWM2≠ FPWM3≠ FPWM4 Buck Waveforms for -3Note Only three bucks shown here 500 Example 3-1. Configuration for Example in FigureControl of Four Buck Stages. Note FPWM2 = N x FPWM1 Controlling Multiple Buck Converters With Same FrequenciesBuck Waveforms for -5Note FPWM2 = FPWM1 Example 3-2. Code Snippet for Configuration in Figure Control of Two Half-H Bridge Stages FPWM2 = N x FPWM1 Controlling Multiple Half H-Bridge HHB ConvertersHalf-H Bridge Waveforms for -7Note Here FPWM2 = FPWM1 Example 3-3. Code Snippet for Configuration in Figure Controlling Dual 3-Phase Inverters for Motors ACI and PmsmEPWM1A 10 -Phase Inverter Waveforms for -9Only One Inverter Shown Example 3-4. Code Snippet for Configuration in Figure 11. Configuring Two PWM Modules for Phase Control Controlling a 3-Phase Interleaved DC/DC Converter Controlling a 3-Phase Interleaved DC/DC Converter13. Control of a 3-Phase Interleaved DC/DC Converter 14 -Phase Interleaved DC/DC Converter Waveforms for Figure Example 3-5. Code Snippet for Configuration in Figure 15. Controlling a Full-H Bridge Stage FPWM2 = FPWM1 16. ZVS Full-H Bridge Waveforms Example 3-6. Code Snippet for Configuration in Figure Submit Documentation Feedback Proper Interrupt Initialization Procedure PWM-Chopper Submodule Control RegisterTrip-Zone Submodule Control and Status Registers Time-Base Submodule Registers Time-Base Phase Register Tbphs Field DescriptionsTime-Base Period Register Tbprd Field Descriptions Time-Base Counter Register Tbctr Field DescriptionsBit Field Value Description Time-Base Control Register Tbctl Field DescriptionsSoftware Forced Synchronization Pulse Counter-Compare Submodule Registers Time-Base Status Register Tbsts Field DescriptionsBit Field Counter-Compare a Register Cmpa Field Descriptions Counter-Compare B Register Cmpb Field DescriptionsBits Name Description Counter-Compare Control Register Cmpctl Field Descriptions Action-Qualifier Submodule RegistersCBD CBU CAD CAU PRD ZRO Bits NameCBD 10. Action-Qualifier Output B Control Register Aqctlb Rldcsf Otsfb Actsfb Otsfa Actsfa RldcsfCsfb Csfa Dead-Band Submodule Registers CsfbInmode Polsel Outmode Inmode 16. PWM-Chopper Control Register Pcctl Bit Descriptions PWM-Chopper Submodule Control RegisterName Value Description ReservedTrip-Zone Submodule Control and Status Registers PWM-Chopper Control Register Pcctl Bit DescriptionsChpduty CBC6 CBC5 CBC4 CBC3 CBC2 CBC1 OSHT6 OSHT5 OSHT4 OSHT3 OSHT2 OSHT1OSHT6 CBC6TZB TZA 18. Trip-Zone Control Register Tzctl Field DescriptionsTZB OST CBCOST CBC INT 20. Trip-Zone Flag Register Tzflg Field DescriptionsEvent-Trigger Submodule Registers 21. Trip-Zone Clear Register Tzclr Field Descriptions22. Trip-Zone Force Register Tzfrc Field Descriptions 23. Event-Trigger Selection Register Etsel Name Description 24. Event-Trigger Prescale Register Etps Field DescriptionsSocb Soca 24. Event-Trigger Prescale Register Etps Field Descriptions25. Event-Trigger Flag Register Etflg Field Descriptions 26. Event-Trigger Clear Register Etclr Field DescriptionsSocb 27. Event-Trigger Force Register Etfrc Field Descriptions Proper Interrupt Initialization Procedure116 Location Modifications, Additions, and Deletions Table A-1. Changes for Revision DAppendix a Important Notice
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