Texas Instruments TMS320C6457 manual HR/WI Hhwili Hasi, Hstrb

Page 10

Introduction to the HPI

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Signal

State (1)

HCNTL[1:0] I

HR/WI

HHWILI

HASI

 

HD[31:0]

I/O/Z

 

HD[15:0]

 

 

 

 

 

 

 

 

 

O/Z

 

HRDY

 

 

 

 

 

 

 

 

 

O/Z

 

HINT

Table 2. HPI Signals

(continued)

 

 

 

Host Connection

 

Description

 

 

 

Address or control pins

 

The HPI latches the logic levels of these pins on the

 

 

falling edge of

HAS

or internal

HSTRB

(for details

 

 

about internal

HSTRB,

see Section 3.3). The four

 

 

binary states of these pins determine the access type

 

 

of the current transfer (HPIC, HPID with

 

 

autoincrementing, HPIA, or HPID without

 

 

autoincrementing).

 

 

 

 

 

 

 

 

 

 

R/W strobe pin

 

HPI read/write. On the falling edge of

 

 

or internal

 

HAS

 

 

 

 

 

 

indicates whether the current access is

 

 

HSTRB,

HR/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

high

 

 

to be a read or write operation. Driving HR/W

 

 

indicates the transfer is a read from the HPI, while

 

 

 

 

 

low indicates a write to the HPI.

 

 

driving HR/W

Address or control pins

 

Halfword identification control input. This bit identifies

 

 

the first and second halfwords of a dual halfword cycle

 

 

operation. HHWIL=0 identifies the first cycle and

 

 

HHWIL=1 identifies the second cycle. HHWIL applies

 

 

only to HPI16 mode and not to HPI32 mode.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ALE (address latch enable) or

 

Address strobe. A host with a multiplexed address/data

address strobe pin

 

bus can have

HAS

 

connected to its ALE pin. The

 

 

falling edge of

HAS

 

latches the logic levels of the

 

 

 

 

HCNTL1, and HCNTL0 pins, which are typically

 

 

HR/W,

 

 

connected to host address lines. When used, the

HAS

 

 

 

signal must precede the falling edge of the internal

 

 

HSTRB

signal.

Data bus

 

The HPI data bus carries the data to/from the HPI.

 

 

HD[31:0] applies to HPI32 and HD[15:0] applies to

 

 

HPI16.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Asynchronous ready pin

 

When the HPI drives

 

 

low, the host has

HRDY

 

 

permission to complete the current host cycle. When

 

 

the HPI drives

HRDY

 

high, the HPI is not ready for the

 

 

current host cycle to complete.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Interrupt pin

 

The DSP can interrupt the host processor by writing a

 

 

1 to the HINT bit of HPIC. Before subsequent HINT

 

 

interrupts can occur, the host must clear previous

 

 

interrupts by writing a 1 to the HINT bit. This pin is

 

 

active-low and inverted from the HINT bit value in

 

 

HPIC.

10

Host Port Interface (HPI)

SPRUGK7A –March 2009 –Revised July 2010

Copyright © 2009–2010, Texas Instruments Incorporated

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Contents Users Guide SPRUGK7A -March 2009 -Revised July HDS2 HDS1 HCS Appendix aHas List of Figures List of Tables Notational Conventions About This ManualRelated Documentation From Texas Instruments Introduction to the HPI Summary of the HPI Registers HPI Signals Summary of the HPI SignalsSummary of HPI Registers HR/WI Hhwili Hasi HstrbSingle-HPIA Mode Using the Address RegistersDual-HPIA Mode Host-HPI Signal Connections HPI OperationHhwil HPI Configuration and Data Flow Available Host Data Strobe Pins Options for Connecting Host and HPI Data Strobe PinsHDS2, HDS1, and HCS Data Strobing and Chip Selection HCNTL10 and HR/W Indicating the Cycle Type Access Types Selectable by the Hcntl SignalsCycle Types Selectable With the Hcntl and HR/W Signals Cycle TypeHas Forcing the HPI to Latch Control Information Early HCS Has Hrdy a HhwilHCS Has HR/W Hrdya HhwilPerforming a Multiplexed Access Without has Hstrb HR/WBit Multiplexed Mode Host Write Cycle With has Tied High Single-Halfword Hpic Cycle in the 16-Bit Multiplexed Mode Hardware Handshaking Using the HPI-Ready Hrdy SignalHrdy Behavior During 16-Bit Multiplexed Read Operations HrdyHrdy Behavior During 16-Bit Multiplexed Write Operations HR/W HhwilHrdy Behavior During 32-Bit Multiplexed Read Operations Hpid Read Hrdy Behavior During 32-Bit Multiplexed Write OperationsHpia Write Hpia Write HPID+ ReadsHpia Write Hpid Write Hpia Write HPID+ Writes Software Handshaking Using the HPI Ready Hrdy Bit Polling the Hrdy BitHint Bit CPU-to-Host Interrupts Interrupts Between the Host and the CPUDspint Bit Host-to-CPU Interrupts DSPINT=0CPU-to-Host Interrupt State Diagram FIFOs and Bursting Read BurstingWrite Bursting Fifo Behavior When a Hardware Reset or Software Reset Occurs Fifo Flush ConditionsHardware Reset Considerations Emulation and Reset ConsiderationsSoftware Reset Considerations Emulation ModesIntroduction HPI RegistersHost Port Interface HPI Registers Bit Field Value Description Power and Emulation Management Register PwremumgmtSoft Free R/W-0 R/W-0 SoftHost Port Interface Control Register Hpic For host write cycle DualhpiaFetch HPID/HPIC/HPIAR/HPIAWAddress Host Port Interface Address Registers Hpiaw and HpiarBit Field Value Description 31-0 Data Data Register HpidData Register Hpid Field Descriptions HPI dataTMS320C6457 HPI Revision History Appendix a Revision HistorySeeAdditions/Modifications/Deletions Products Applications Rfid

TMS320C6457 specifications

The Texas Instruments TMS320C6457 is a high-performance digital signal processor (DSP) designed for demanding applications in telecommunications, industrial control, and video processing. As part of the TMS320C6000 family, the C6457 combines advanced features with impressive processing capabilities, making it a popular choice among developers looking for efficient and robust solutions.

One of the key features of the TMS320C6457 is its architecture, which is based on the super Harvard architecture. This design separates program and data memory paths, allowing for parallel instruction execution. The C6457 operates at clock speeds of up to 1 GHz, enabling it to deliver peak performance of over 6,000 MIPS (Million Instructions Per Second) and 12,000 MADDs (Multiply-Accumulate operations per second). Such high throughput makes the C6457 suitable for real-time processing applications that require rapid data handling.

The C6457 DSP integrates a rich set of on-chip resources, including up to 1MB of on-chip SRAM, which serves as a fast cache for data and instructions. The device features multiple high-speed interfaces, such as 10/100/1000 Ethernet, Serial RapidIO, and PCI-Express, facilitating seamless connectivity with other devices and systems. Furthermore, the TMS320C6457 supports various communication protocols, allowing it to adapt to a wide range of application scenarios.

In terms of power efficiency, the TMS320C6457 is designed with sophisticated power management features. It includes dynamic voltage and frequency scaling, which adjust power consumption based on workload requirements without compromising performance. This capability is particularly valuable in battery-operated devices or environments where thermal management is critical.

The TMS320C6457 also benefits from extensive software support, including the Texas Instruments DSP/BIOS real-time operating system and Code Composer Studio integrated development environment. Developers can leverage these tools for efficient code development, debugging, and system optimization. Additionally, Texas Instruments provides a range of libraries and algorithms optimized for the C6457, facilitating rapid application development.

Overall, the Texas Instruments TMS320C6457 DSP stands out due to its robust architecture, high processing capabilities, comprehensive connectivity options, and power management features. These attributes make it a versatile solution for a broad spectrum of applications in digital signal processing, where performance and efficiency are paramount. As technology continues to advance, the TMS320C6457 remains a relevant and potent option for developers seeking to push the boundaries of digital signal processing.
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