Texas Instruments TMS320C6457 manual Has Forcing the HPI to Latch Control Information Early

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HPI Operation

3.5HHWIL: Identifying the First and Second Halfwords in 16-Bit Multiplexed Mode

In the 16-bit multiplexed mode, each host cycle consists of two consecutive halfword transfers. For each transfer, the host must specify the cycle type with HCNTL[1:0] and HR/W, and the host must use HHWIL to indicate whether the first or second halfword is being transferred. For HPID and HPIA accesses, HHWIL must always be driven low for the first halfword transfer and high for the second halfword transfer. Results are undefined if the sequence is broken. For examples of HHWIL usage, see the figures in Section 3.6 and Section 3.7.

When the host sends the two halfwords of a 32-bit word in this manner, the host can send the most and least significant halfwords of the 32-bit word in either order (most significant halfword first or most significant halfword second). However, the host must inform the HPI of the selected order before beginning the host cycle. This is done by programming the halfword order (HWOB) bit of HPIC. Although (HWOB) is written at bit 0 in HPIC, its current value is readable at both bit 0 and bit 8 (HWOBSTAT). Thus, the host can determine the current halfword-order configuration by checking the least significant bit of either half of HPIC.

There is one case when the 16-bit multiplexed mode does not require a dual-halfword cycle with HHWIL low for the first halfword and HHWIL high for the second halfword. The least significant 16 bits of the HPIC register can be accessed with a single-halfword cycle. During such a cycle, the host can drive HHWIL either high or low. Either approach returns the same value. Section 3.9 includes an example timing diagram of this case.

In the 32-bit multiplexed mode, each host cycle is one word transfer. The HHWIL signal is ignored and 32 bits of data transferred for each active cycle of the internal strobe signal (internal HSTRB).

3.6HAS: Forcing the HPI to Latch Control Information Early

The HAS signal is an address strobe that allows control information to be removed earlier in a host cycle, allowing more time to switch bus states from address to data information. This feature facilitates the interface for multiplexed address and data buses. In this type of system, an address latch enable (ALE) signal is often provided and is normally the signal connected to HAS.

Figure 2 and Figure 4 show examples of signal connections when HAS is used for multiplexed transfers. Figure 7 and Figure 8 show typical HPI signal activity when HAS is used. The process for using HAS is as follows:

1.The host selects the access type. The host drives the appropriate levels on the HCNTL [1:0] and HR/W signals, and indicates which halfword (first or second) will be transferred by driving HHWIL high or low.

2.The host drives HAS low. On the falling edge of HAS, the HPI latches the states of the HCNTL[1:0], HR/W, and HHWIL. The high to low transition of HAS must precede the falling edge of the internal strobe signal (internal HSTRB), which is derived from HCS, HDS1, and HDS2, as described in Section 3.3.

HCS does not gate the HAS input, which allows time for the host to perform the subsequent access. The HAS signal may be brought high after internal HSTRB goes low, indicating that the data access is about to occur. HAS is not required to be driven high at any time during the cycle, but eventually must transition high before the host uses it for another access with different values for HCNTL [1:0], HR/W, and HHWIL.

SPRUGK7A –March 2009 –Revised July 2010

Host Port Interface (HPI)

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Copyright © 2009–2010, Texas Instruments Incorporated

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Contents Users Guide SPRUGK7A -March 2009 -Revised July Has Appendix aHDS2 HDS1 HCS List of Figures List of Tables Related Documentation From Texas Instruments About This ManualNotational Conventions Introduction to the HPI Summary of the HPI Registers Summary of HPI Registers Summary of the HPI SignalsHPI Signals Hstrb HR/WI Hhwili HasiDual-HPIA Mode Using the Address RegistersSingle-HPIA Mode HPI Operation Host-HPI Signal ConnectionsHhwil HPI Configuration and Data Flow HDS2, HDS1, and HCS Data Strobing and Chip Selection Options for Connecting Host and HPI Data Strobe PinsAvailable Host Data Strobe Pins Cycle Types Selectable With the Hcntl and HR/W Signals Access Types Selectable by the Hcntl SignalsHCNTL10 and HR/W Indicating the Cycle Type Cycle TypeHas Forcing the HPI to Latch Control Information Early Hrdy a Hhwil HCS HasHrdya Hhwil HCS Has HR/WHstrb HR/W Performing a Multiplexed Access Without hasBit Multiplexed Mode Host Write Cycle With has Tied High Hardware Handshaking Using the HPI-Ready Hrdy Signal Single-Halfword Hpic Cycle in the 16-Bit Multiplexed ModeHrdy Hrdy Behavior During 16-Bit Multiplexed Read OperationsHR/W Hhwil Hrdy Behavior During 16-Bit Multiplexed Write OperationsHrdy Behavior During 32-Bit Multiplexed Read Operations Hpia Write Hrdy Behavior During 32-Bit Multiplexed Write OperationsHpid Read Hpia Write HPID+ ReadsHpia Write Hpid Write Hpia Write HPID+ Writes Polling the Hrdy Bit Software Handshaking Using the HPI Ready Hrdy BitDspint Bit Host-to-CPU Interrupts Interrupts Between the Host and the CPUHint Bit CPU-to-Host Interrupts DSPINT=0CPU-to-Host Interrupt State Diagram Read Bursting FIFOs and BurstingWrite Bursting Fifo Flush Conditions Fifo Behavior When a Hardware Reset or Software Reset OccursSoftware Reset Considerations Emulation and Reset ConsiderationsHardware Reset Considerations Emulation ModesHost Port Interface HPI Registers HPI RegistersIntroduction Soft Free R/W-0 R/W-0 Power and Emulation Management Register PwremumgmtBit Field Value Description SoftHost Port Interface Control Register Hpic Fetch DualhpiaFor host write cycle HPID/HPIC/HPIAR/HPIAWBit Field Value Description 31-0 Host Port Interface Address Registers Hpiaw and HpiarAddress Data Register Hpid Field Descriptions Data Register HpidData HPI dataSeeAdditions/Modifications/Deletions Appendix a Revision HistoryTMS320C6457 HPI Revision History Rfid Products Applications

TMS320C6457 specifications

The Texas Instruments TMS320C6457 is a high-performance digital signal processor (DSP) designed for demanding applications in telecommunications, industrial control, and video processing. As part of the TMS320C6000 family, the C6457 combines advanced features with impressive processing capabilities, making it a popular choice among developers looking for efficient and robust solutions.

One of the key features of the TMS320C6457 is its architecture, which is based on the super Harvard architecture. This design separates program and data memory paths, allowing for parallel instruction execution. The C6457 operates at clock speeds of up to 1 GHz, enabling it to deliver peak performance of over 6,000 MIPS (Million Instructions Per Second) and 12,000 MADDs (Multiply-Accumulate operations per second). Such high throughput makes the C6457 suitable for real-time processing applications that require rapid data handling.

The C6457 DSP integrates a rich set of on-chip resources, including up to 1MB of on-chip SRAM, which serves as a fast cache for data and instructions. The device features multiple high-speed interfaces, such as 10/100/1000 Ethernet, Serial RapidIO, and PCI-Express, facilitating seamless connectivity with other devices and systems. Furthermore, the TMS320C6457 supports various communication protocols, allowing it to adapt to a wide range of application scenarios.

In terms of power efficiency, the TMS320C6457 is designed with sophisticated power management features. It includes dynamic voltage and frequency scaling, which adjust power consumption based on workload requirements without compromising performance. This capability is particularly valuable in battery-operated devices or environments where thermal management is critical.

The TMS320C6457 also benefits from extensive software support, including the Texas Instruments DSP/BIOS real-time operating system and Code Composer Studio integrated development environment. Developers can leverage these tools for efficient code development, debugging, and system optimization. Additionally, Texas Instruments provides a range of libraries and algorithms optimized for the C6457, facilitating rapid application development.

Overall, the Texas Instruments TMS320C6457 DSP stands out due to its robust architecture, high processing capabilities, comprehensive connectivity options, and power management features. These attributes make it a versatile solution for a broad spectrum of applications in digital signal processing, where performance and efficiency are paramount. As technology continues to advance, the TMS320C6457 remains a relevant and potent option for developers seeking to push the boundaries of digital signal processing.
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