Texas Instruments TMS320C6457 manual Hrdy Behavior During 16-Bit Multiplexed Read Operations

Page 23

www.ti.com

HPI Operation

The following sections describe the behavior of HRDY during HPI register accesses. In all cases, the chip select signal, HCS, must be asserted for HRDY to go high.

3.9.1HRDY Behavior During 16-Bit Multiplexed Read Operations

Figure 12 shows an HPIC (HCNTL[1:0] = 00b) or HPIA (HCNTL[1:0] = 10b) read cycle during 16-bit multiplexed HPI operation. Neither an HPIC read cycle nor an HPIA read cycle causes HRDY to go high.

Figure 12. HRDY Behavior During an HPIC or HPIA Read Cycle in the 16-Bit Multiplexed Mode

HCS

HCNTL[1:0] 00 or 10 00 or 10

HR/W

HHWIL

Internal

HSTRB

HD[15:0] 1st halfword 2nd halfword

HRDY

Figure 13 includes an HPID read cycle without autoincrementing in the 16-bit multiplexed mode. The host writes the memory address during the HPIA (HCNTL[1:0] = 10b) write cycle, and the host reads the data during the HPID (HCNTL[1:0] = 11b) read cycle. HRDY goes high for each HPIA halfword access, but HRDY goes high for only the first halfword access in each HPID read cycle.

Figure 13. HRDY Behavior During a Data Read Operation in the 16-Bit Multiplexed Mode

(Case 1: HPIA Write Cycle Followed by Nonautoincrement HPID Read Cycle)

HPIA write

HCS

HPID read

HCNTL[1:0] 10 10 11 11

HR/W

HHWIL

Internal

 

 

 

 

HSTRB

1st halfword

2nd halfword

1st halfword

2nd halfword

 

HD[15:0]

 

 

 

 

HRDY

 

 

 

 

Figure 14 includes an autoincrement HPID read cycle in the 16-bit multiplexed mode. The host writes the memory address while asserting HCNTL[1:0] = 10b and reads the data while asserting HCNTL[1:0] = 01b. During the first HPID read cycle, HRDY goes high for only the first halfword access, and subsequent HPID read cycles do not cause HRDY to go high.

Figure 14. HRDY Behavior During a Data Read Operation in the 16-Bit Multiplexed Mode

(Case 2: HPIA Write Cycle Followed by Autoincrement HPID Read Cycles)

HPIA write

HCS

HPID+ reads

HCNTL[1:0] 10 10 01 01 01

HR/W

 

 

 

 

 

HHWIL

 

 

 

 

 

Internal

 

 

 

 

 

HSTRB

1st halfword

2nd halfword

1st halfword

2nd halfword

1st halfword

 

HD[15:0]

 

 

 

 

 

HRDY

 

 

 

 

 

SPRUGK7A –March 2009 –Revised July 2010

Host Port Interface (HPI)

23

Copyright © 2009–2010, Texas Instruments Incorporated

Page 22 Page 24
Image 23
Page 22 Page 24
Contents Users Guide SPRUGK7A -March 2009 -Revised July Has Appendix aHDS2 HDS1 HCS List of Figures List of Tables Related Documentation From Texas Instruments About This ManualNotational Conventions Introduction to the HPI Summary of the HPI Registers Summary of HPI Registers Summary of the HPI SignalsHPI Signals Hstrb HR/WI Hhwili HasiDual-HPIA Mode Using the Address RegistersSingle-HPIA Mode HPI Operation Host-HPI Signal ConnectionsHhwil HPI Configuration and Data Flow HDS2, HDS1, and HCS Data Strobing and Chip Selection Options for Connecting Host and HPI Data Strobe PinsAvailable Host Data Strobe Pins Cycle Type Access Types Selectable by the Hcntl SignalsCycle Types Selectable With the Hcntl and HR/W Signals HCNTL10 and HR/W Indicating the Cycle TypeHas Forcing the HPI to Latch Control Information Early Hrdy a Hhwil HCS HasHrdya Hhwil HCS Has HR/WHstrb HR/W Performing a Multiplexed Access Without hasBit Multiplexed Mode Host Write Cycle With has Tied High Hardware Handshaking Using the HPI-Ready Hrdy Signal Single-Halfword Hpic Cycle in the 16-Bit Multiplexed ModeHrdy Hrdy Behavior During 16-Bit Multiplexed Read OperationsHR/W Hhwil Hrdy Behavior During 16-Bit Multiplexed Write OperationsHrdy Behavior During 32-Bit Multiplexed Read Operations Hpia Write HPID+ Reads Hrdy Behavior During 32-Bit Multiplexed Write OperationsHpia Write Hpid ReadHpia Write Hpid Write Hpia Write HPID+ Writes Polling the Hrdy Bit Software Handshaking Using the HPI Ready Hrdy BitDSPINT=0 Interrupts Between the Host and the CPUDspint Bit Host-to-CPU Interrupts Hint Bit CPU-to-Host InterruptsCPU-to-Host Interrupt State Diagram Read Bursting FIFOs and BurstingWrite Bursting Fifo Flush Conditions Fifo Behavior When a Hardware Reset or Software Reset OccursEmulation Modes Emulation and Reset ConsiderationsSoftware Reset Considerations Hardware Reset ConsiderationsHost Port Interface HPI Registers HPI RegistersIntroduction Soft Power and Emulation Management Register PwremumgmtSoft Free R/W-0 R/W-0 Bit Field Value DescriptionHost Port Interface Control Register Hpic HPID/HPIC/HPIAR/HPIAW DualhpiaFetch For host write cycleBit Field Value Description 31-0 Host Port Interface Address Registers Hpiaw and HpiarAddress HPI data Data Register HpidData Register Hpid Field Descriptions DataSeeAdditions/Modifications/Deletions Appendix a Revision HistoryTMS320C6457 HPI Revision History Rfid Products Applications

TMS320C6457 specifications

The Texas Instruments TMS320C6457 is a high-performance digital signal processor (DSP) designed for demanding applications in telecommunications, industrial control, and video processing. As part of the TMS320C6000 family, the C6457 combines advanced features with impressive processing capabilities, making it a popular choice among developers looking for efficient and robust solutions.

One of the key features of the TMS320C6457 is its architecture, which is based on the super Harvard architecture. This design separates program and data memory paths, allowing for parallel instruction execution. The C6457 operates at clock speeds of up to 1 GHz, enabling it to deliver peak performance of over 6,000 MIPS (Million Instructions Per Second) and 12,000 MADDs (Multiply-Accumulate operations per second). Such high throughput makes the C6457 suitable for real-time processing applications that require rapid data handling.

The C6457 DSP integrates a rich set of on-chip resources, including up to 1MB of on-chip SRAM, which serves as a fast cache for data and instructions. The device features multiple high-speed interfaces, such as 10/100/1000 Ethernet, Serial RapidIO, and PCI-Express, facilitating seamless connectivity with other devices and systems. Furthermore, the TMS320C6457 supports various communication protocols, allowing it to adapt to a wide range of application scenarios.

In terms of power efficiency, the TMS320C6457 is designed with sophisticated power management features. It includes dynamic voltage and frequency scaling, which adjust power consumption based on workload requirements without compromising performance. This capability is particularly valuable in battery-operated devices or environments where thermal management is critical.

The TMS320C6457 also benefits from extensive software support, including the Texas Instruments DSP/BIOS real-time operating system and Code Composer Studio integrated development environment. Developers can leverage these tools for efficient code development, debugging, and system optimization. Additionally, Texas Instruments provides a range of libraries and algorithms optimized for the C6457, facilitating rapid application development.

Overall, the Texas Instruments TMS320C6457 DSP stands out due to its robust architecture, high processing capabilities, comprehensive connectivity options, and power management features. These attributes make it a versatile solution for a broad spectrum of applications in digital signal processing, where performance and efficiency are paramount. As technology continues to advance, the TMS320C6457 remains a relevant and potent option for developers seeking to push the boundaries of digital signal processing.
Top Page Image Contents