Texas Instruments TMS320C6457 manual Interrupts Between the Host and the CPU, DSPINT=0

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Interrupts Between the Host and the CPU

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5Interrupts Between the Host and the CPU

The host can interrupt the CPU of the DSP via the DSPINT bit of the HPIC, as described in Section 5.1. The CPU can send an interrupt to the host by using the HINT bit of HPIC, as described in Section 5.2.

5.1DSPINT Bit: Host-to-CPU Interrupts

The DSPINT bit of HPIC allows the host to send an interrupt request to the CPU, as summarized in Figure 26 and detailed following the figure.

Figure 26. Host-to-CPU Interrupt State Diagram

Host writes 0 to DSPINT bit

Host writes 1 to DSPINT bit

(interrupt generated to CPU)(A)

Host writes 0 or 1 to DSPINT bit

No interrupt/

 

interrupt

 

cleared

CPU writes 0 or 1

 

to DSPINT bit

DSPINT=0

 

 

CPU writes 1

 

to DSPINT bit

Interrupt

 

pending

 

DSPINT=1

CPU writes 0 to DSPINT bit

AWhen the DSPINT bit transitions from 0 to 1, an interrupt is generated to the CPU. No new interrupt can be generated until the CPU has cleared the bit (DSPINT = 0).

To interrupt the CPU, the host must:

1.Drive both HCNTL1 and HCNTL0 low to request a write to HPIC.

2.Write 1 to the DSPINT bit in HPIC.

When the host sets the DSPINT bit, the HPI generates an interrupt pulse to the CPU that sets the corresponding flag bit in an interrupt flag register of the CPU. If this maskable interrupt is properly enabled in the CPU, the CPU executes the corresponding interrupt service routine (ISR). Before the host can use DSPINT to generate a subsequent interrupt to the CPU, the CPU must acknowledge the current interrupt by writing a 1 to the DSPINT bit. When the CPU writes 1, DSPINT is forced to 0. The host should verify that DSPINT = 0 before generating subsequent interrupts. While DSPINT = 1, host writes to the DSPINT bit do not generate an interrupt pulse.

Writes of 0 have no effect on the DSPINT bit. A hardware reset immediately clears DSPINT and thus clears an active host-to-CPU interrupt.

5.2HINT Bit: CPU-to-Host Interrupts

The HINT bit of HPIC allows the CPU to send an interrupt request to the host, as summarized in Figure 27 and detailed following the figure.

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Host Port Interface (HPI)

SPRUGK7A –March 2009 –Revised July 2010

Copyright © 2009–2010, Texas Instruments Incorporated

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Contents Users Guide SPRUGK7A -March 2009 -Revised July Appendix a HDS2 HDS1 HCSHas List of Figures List of Tables About This Manual Notational ConventionsRelated Documentation From Texas Instruments Introduction to the HPI Summary of the HPI Registers Summary of the HPI Signals HPI SignalsSummary of HPI Registers HR/WI Hhwili Hasi HstrbUsing the Address Registers Single-HPIA ModeDual-HPIA Mode Host-HPI Signal Connections HPI OperationHhwil HPI Configuration and Data Flow Options for Connecting Host and HPI Data Strobe Pins Available Host Data Strobe PinsHDS2, HDS1, and HCS Data Strobing and Chip Selection HCNTL10 and HR/W Indicating the Cycle Type Access Types Selectable by the Hcntl SignalsCycle Types Selectable With the Hcntl and HR/W Signals Cycle TypeHas Forcing the HPI to Latch Control Information Early HCS Has Hrdy a HhwilHCS Has HR/W Hrdya HhwilPerforming a Multiplexed Access Without has Hstrb HR/WBit Multiplexed Mode Host Write Cycle With has Tied High Single-Halfword Hpic Cycle in the 16-Bit Multiplexed Mode Hardware Handshaking Using the HPI-Ready Hrdy SignalHrdy Behavior During 16-Bit Multiplexed Read Operations HrdyHrdy Behavior During 16-Bit Multiplexed Write Operations HR/W HhwilHrdy Behavior During 32-Bit Multiplexed Read Operations Hpid Read Hrdy Behavior During 32-Bit Multiplexed Write OperationsHpia Write Hpia Write HPID+ ReadsHpia Write Hpid Write Hpia Write HPID+ Writes Software Handshaking Using the HPI Ready Hrdy Bit Polling the Hrdy BitHint Bit CPU-to-Host Interrupts Interrupts Between the Host and the CPUDspint Bit Host-to-CPU Interrupts DSPINT=0CPU-to-Host Interrupt State Diagram FIFOs and Bursting Read BurstingWrite Bursting Fifo Behavior When a Hardware Reset or Software Reset Occurs Fifo Flush ConditionsHardware Reset Considerations Emulation and Reset ConsiderationsSoftware Reset Considerations Emulation ModesHPI Registers IntroductionHost Port Interface HPI Registers Bit Field Value Description Power and Emulation Management Register PwremumgmtSoft Free R/W-0 R/W-0 SoftHost Port Interface Control Register Hpic For host write cycle DualhpiaFetch HPID/HPIC/HPIAR/HPIAWHost Port Interface Address Registers Hpiaw and Hpiar AddressBit Field Value Description 31-0 Data Data Register HpidData Register Hpid Field Descriptions HPI dataAppendix a Revision History TMS320C6457 HPI Revision HistorySeeAdditions/Modifications/Deletions Products Applications Rfid

TMS320C6457 specifications

The Texas Instruments TMS320C6457 is a high-performance digital signal processor (DSP) designed for demanding applications in telecommunications, industrial control, and video processing. As part of the TMS320C6000 family, the C6457 combines advanced features with impressive processing capabilities, making it a popular choice among developers looking for efficient and robust solutions.

One of the key features of the TMS320C6457 is its architecture, which is based on the super Harvard architecture. This design separates program and data memory paths, allowing for parallel instruction execution. The C6457 operates at clock speeds of up to 1 GHz, enabling it to deliver peak performance of over 6,000 MIPS (Million Instructions Per Second) and 12,000 MADDs (Multiply-Accumulate operations per second). Such high throughput makes the C6457 suitable for real-time processing applications that require rapid data handling.

The C6457 DSP integrates a rich set of on-chip resources, including up to 1MB of on-chip SRAM, which serves as a fast cache for data and instructions. The device features multiple high-speed interfaces, such as 10/100/1000 Ethernet, Serial RapidIO, and PCI-Express, facilitating seamless connectivity with other devices and systems. Furthermore, the TMS320C6457 supports various communication protocols, allowing it to adapt to a wide range of application scenarios.

In terms of power efficiency, the TMS320C6457 is designed with sophisticated power management features. It includes dynamic voltage and frequency scaling, which adjust power consumption based on workload requirements without compromising performance. This capability is particularly valuable in battery-operated devices or environments where thermal management is critical.

The TMS320C6457 also benefits from extensive software support, including the Texas Instruments DSP/BIOS real-time operating system and Code Composer Studio integrated development environment. Developers can leverage these tools for efficient code development, debugging, and system optimization. Additionally, Texas Instruments provides a range of libraries and algorithms optimized for the C6457, facilitating rapid application development.

Overall, the Texas Instruments TMS320C6457 DSP stands out due to its robust architecture, high processing capabilities, comprehensive connectivity options, and power management features. These attributes make it a versatile solution for a broad spectrum of applications in digital signal processing, where performance and efficiency are paramount. As technology continues to advance, the TMS320C6457 remains a relevant and potent option for developers seeking to push the boundaries of digital signal processing.
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