Texas Instruments TMS320C6457 manual HPI Configuration and Data Flow

Page 14

HPI Operation

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Figure 5. Example of Host-DSP Signal Connections When the HAS Signal is Tied High in the 16-Bit

Multiplexed Mode

Host

Address or I/O

Read/Write

Chip select

Data strobeA

Data

Ready

Interrupt

Logic high

Logic high

No connect

2

16

16

DSP

HPI

HAS

HCNTL[1:0]

HHWIL

HR/W

HCS

HDS1

HDS2

HD[31:16]

HD[15:0]

HRDY

HINT

AData strobing options are given in Section 3.3.

3.2HPI Configuration and Data Flow

In multiplexed mode, the HPIC and HPIA must be initialized before valid host access cycles can take place. The CPU and host must follow these steps to configure the HPI initially:

1.The CPU clears the HPIRST bit in the HPI register. All host accesses will be held off by the deassertion of HRDY until HPIRST is cleared.

2.After the HPIRST bit is cleared, the host writes the HPIC register to program the halfword ordering bit (HWOB) and the HPIA-related bits (DUALHPIA and HPIARWSEL). The HWOB bit must be programmed before any accesses to the HPID and HPIA registers because this bit defines the ordering of all halfword accesses in the 16-bit multiplexed mode.

3.The host writes the desired internal DSP word address to an address register (HPIAR and/or HPIAW). Section 2 introduces the two HPIA registers and their interaction with the host.

4.The host either reads from or writes to the data register (HPID). Data transfers between HPID and the internal resources of the DSP are handled by the HPI DMA logic.

Each step of the access uses the same bus. Therefore, the host must drive the appropriate levels on the HCNTL1 and HCNTL0 signals to indicate which register is to be accessed. The host must also drive the appropriate level on the HR/W signal to indicate the data direction (read or write) and must drive other control signals as appropriate. When HPI resources are temporarily busy or unavailable, the HPI informs the host by deasserting the HPI-ready (HRDY) output signal.

When performing an access, the HPI first latches the levels on HCNTL[1:0], HR/W, and other control signals. This latching can occur on the falling edge of the internal strobe signal (see Section 3.3) or the falling edge of HAS (see Section 3.6). After the control information is latched, the HPI initiates an access based on the control signals.

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Host Port Interface (HPI)

SPRUGK7A –March 2009 –Revised July 2010

Copyright © 2009–2010, Texas Instruments Incorporated

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Contents Users Guide SPRUGK7A -March 2009 -Revised July Has Appendix aHDS2 HDS1 HCS List of Figures List of Tables Related Documentation From Texas Instruments About This ManualNotational Conventions Introduction to the HPI Summary of the HPI Registers Summary of HPI Registers Summary of the HPI SignalsHPI Signals HR/WI Hhwili Hasi HstrbDual-HPIA Mode Using the Address RegistersSingle-HPIA Mode Host-HPI Signal Connections HPI OperationHhwil HPI Configuration and Data Flow HDS2, HDS1, and HCS Data Strobing and Chip Selection Options for Connecting Host and HPI Data Strobe PinsAvailable Host Data Strobe Pins HCNTL10 and HR/W Indicating the Cycle Type Access Types Selectable by the Hcntl SignalsCycle Types Selectable With the Hcntl and HR/W Signals Cycle TypeHas Forcing the HPI to Latch Control Information Early HCS Has Hrdy a HhwilHCS Has HR/W Hrdya HhwilPerforming a Multiplexed Access Without has Hstrb HR/WBit Multiplexed Mode Host Write Cycle With has Tied High Single-Halfword Hpic Cycle in the 16-Bit Multiplexed Mode Hardware Handshaking Using the HPI-Ready Hrdy SignalHrdy Behavior During 16-Bit Multiplexed Read Operations HrdyHrdy Behavior During 16-Bit Multiplexed Write Operations HR/W HhwilHrdy Behavior During 32-Bit Multiplexed Read Operations Hpid Read Hrdy Behavior During 32-Bit Multiplexed Write OperationsHpia Write Hpia Write HPID+ ReadsHpia Write Hpid Write Hpia Write HPID+ Writes Software Handshaking Using the HPI Ready Hrdy Bit Polling the Hrdy BitHint Bit CPU-to-Host Interrupts Interrupts Between the Host and the CPUDspint Bit Host-to-CPU Interrupts DSPINT=0CPU-to-Host Interrupt State Diagram FIFOs and Bursting Read BurstingWrite Bursting Fifo Behavior When a Hardware Reset or Software Reset Occurs Fifo Flush ConditionsHardware Reset Considerations Emulation and Reset ConsiderationsSoftware Reset Considerations Emulation ModesHost Port Interface HPI Registers HPI RegistersIntroduction Bit Field Value Description Power and Emulation Management Register PwremumgmtSoft Free R/W-0 R/W-0 SoftHost Port Interface Control Register Hpic For host write cycle DualhpiaFetch HPID/HPIC/HPIAR/HPIAWBit Field Value Description 31-0 Host Port Interface Address Registers Hpiaw and HpiarAddress Data Data Register HpidData Register Hpid Field Descriptions HPI dataSeeAdditions/Modifications/Deletions Appendix a Revision HistoryTMS320C6457 HPI Revision History Products Applications Rfid

TMS320C6457 specifications

The Texas Instruments TMS320C6457 is a high-performance digital signal processor (DSP) designed for demanding applications in telecommunications, industrial control, and video processing. As part of the TMS320C6000 family, the C6457 combines advanced features with impressive processing capabilities, making it a popular choice among developers looking for efficient and robust solutions.

One of the key features of the TMS320C6457 is its architecture, which is based on the super Harvard architecture. This design separates program and data memory paths, allowing for parallel instruction execution. The C6457 operates at clock speeds of up to 1 GHz, enabling it to deliver peak performance of over 6,000 MIPS (Million Instructions Per Second) and 12,000 MADDs (Multiply-Accumulate operations per second). Such high throughput makes the C6457 suitable for real-time processing applications that require rapid data handling.

The C6457 DSP integrates a rich set of on-chip resources, including up to 1MB of on-chip SRAM, which serves as a fast cache for data and instructions. The device features multiple high-speed interfaces, such as 10/100/1000 Ethernet, Serial RapidIO, and PCI-Express, facilitating seamless connectivity with other devices and systems. Furthermore, the TMS320C6457 supports various communication protocols, allowing it to adapt to a wide range of application scenarios.

In terms of power efficiency, the TMS320C6457 is designed with sophisticated power management features. It includes dynamic voltage and frequency scaling, which adjust power consumption based on workload requirements without compromising performance. This capability is particularly valuable in battery-operated devices or environments where thermal management is critical.

The TMS320C6457 also benefits from extensive software support, including the Texas Instruments DSP/BIOS real-time operating system and Code Composer Studio integrated development environment. Developers can leverage these tools for efficient code development, debugging, and system optimization. Additionally, Texas Instruments provides a range of libraries and algorithms optimized for the C6457, facilitating rapid application development.

Overall, the Texas Instruments TMS320C6457 DSP stands out due to its robust architecture, high processing capabilities, comprehensive connectivity options, and power management features. These attributes make it a versatile solution for a broad spectrum of applications in digital signal processing, where performance and efficiency are paramount. As technology continues to advance, the TMS320C6457 remains a relevant and potent option for developers seeking to push the boundaries of digital signal processing.
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