Texas Instruments TMS320C6457 manual Write Bursting

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FIFOs and Bursting

If the host initiates an HPID read cycle with autoincrementing, the HPI DMA logic performs two 4-word burst operations to fill the read FIFO. The host is initially held off by the deassertion of the HRDY signal until data is available to be read from the read FIFO. Once data is available in the read FIFO, the host can read data from the read FIFO by performing subsequent reads of HPID with autoincrementing. Once the initial read has been performed, the HPI DMA logic continues to perform 4-word burst operations to consecutive memory addresses every time there are four empty word locations in the read FIFO. The HPI DMA logic continues to prefetch data to keep the read FIFO full, until the occurrence of an event that causes a read FIFO flush (see Section 6.3).

As mentioned, read bursting may also begin with a FETCH command. The host should always precede the FETCH command with the initialization of the HPIAR register or a non-autoincrement access, so that the read FIFO is flushed beforehand. When the host initiates a FETCH command, the HPI DMA logic begins to prefetch data to keep the read FIFO full, as described in the previous paragraph. The FETCH bit in HPIC does not actually store the value that is written to it; rather, the decoding of a host write of 1 to this bit is considered a FETCH command.

The FETCH command can be helpful if the host does not use the HRDY signal. The host can initiate prefetching by writing 1 to the FETCH bit and then poll the HRDY bit, which is also in HPIC. When the HRDY bit is 1, the host can perform an HPID read cycle. See Section 4 for more details on the HRDY bit.

Both types of continuous or burst reads described previously begin with a write to the HPI address register, which causes a read FIFO flush. This is the typical way of initiating read cycles, because the initial read address needs to be specified.

An HPID read cycle without autoincrementing does not initiate any prefetching activity. Instead, it causes the read FIFO to be flushed and causes the HPI DMA logic to perform a single-word read from the processor memory. As soon as the host activates a read cycle without autoincrementing, prefetching activity ceases until the occurrence of a FETCH command or an autoincrement read cycle. A non-autoincrement read cycle always should be preceded by another non-autoincrement cycle or the direct initialization of HPIAR, so that the read FIFO is flushed beforehand.

6.2Write Bursting

A write to the write address register (HPIAW) causes the write FIFO to be flushed. This means that any write data in the write FIFO is forced to its destination in the processor memory (the HPI DMA logic performs burst operations until the write FIFO is empty). When the FIFO has been flushed, the only action that will cause the HPI DMA logic to perform burst writes is a host write to HPID with autoincrementing. The initial host-write data is stored in the write FIFO. An HPI DMA write is not requested until there are four words in the write FIFO. As soon as four words have been written to the FIFO via the HPID write cycles with autoincrementing, the HPI DMA logic performs a 4-word burst operation to the processor memory. The burst operations continue as long as there are at least four words in the FIFO. If the FIFO becomes full (eight words are waiting in the FIFO), the HPI holds off the host by deasserting HRDY until at least one empty word location is available in the FIFO.

Because excessive time might pass between consecutive burst operations, the HPI has a time-out counter. If there are fewer than four words in the write FIFO and the time-out counter expires, the HPI DMA logic empties the FIFO immediately by performing a 2-word or 3-word burst, or a single-word write, as necessary. Every time new data is written to the write FIFO, the time-out counter is automatically reset to begin its count again. The time-out period is 256 internal clock cycles. See the device-specific data manual to determine how the HPI is clocked on your device.

An HPID write cycle without autoincrementing does not initiate any bursting activity. Instead, it causes the write FIFO to be flushed and causes the HPI DMA logic to perform a single-word write to the processor memory. As soon as the host activates a write cycle without autoincrementing, bursting activity ceases until the occurrence of an autoincrement write cycle. A non-autoincrement write cycle always should be preceded by the initialization of HPIAW or by another non-autoincrement access, so that the write FIFO is flushed beforehand.

SPRUGK7A –March 2009 –Revised July 2010

Host Port Interface (HPI)

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Copyright © 2009–2010, Texas Instruments Incorporated

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Contents Users Guide SPRUGK7A -March 2009 -Revised July Appendix a HDS2 HDS1 HCSHas List of Figures List of Tables About This Manual Notational ConventionsRelated Documentation From Texas Instruments Introduction to the HPI Summary of the HPI Registers Summary of the HPI Signals HPI SignalsSummary of HPI Registers Hstrb HR/WI Hhwili HasiUsing the Address Registers Single-HPIA ModeDual-HPIA Mode HPI Operation Host-HPI Signal ConnectionsHhwil HPI Configuration and Data Flow Options for Connecting Host and HPI Data Strobe Pins Available Host Data Strobe PinsHDS2, HDS1, and HCS Data Strobing and Chip Selection Cycle Types Selectable With the Hcntl and HR/W Signals Access Types Selectable by the Hcntl SignalsHCNTL10 and HR/W Indicating the Cycle Type Cycle TypeHas Forcing the HPI to Latch Control Information Early Hrdy a Hhwil HCS HasHrdya Hhwil HCS Has HR/WHstrb HR/W Performing a Multiplexed Access Without hasBit Multiplexed Mode Host Write Cycle With has Tied High Hardware Handshaking Using the HPI-Ready Hrdy Signal Single-Halfword Hpic Cycle in the 16-Bit Multiplexed ModeHrdy Hrdy Behavior During 16-Bit Multiplexed Read OperationsHR/W Hhwil Hrdy Behavior During 16-Bit Multiplexed Write OperationsHrdy Behavior During 32-Bit Multiplexed Read Operations Hpia Write Hrdy Behavior During 32-Bit Multiplexed Write OperationsHpid Read Hpia Write HPID+ ReadsHpia Write Hpid Write Hpia Write HPID+ Writes Polling the Hrdy Bit Software Handshaking Using the HPI Ready Hrdy BitDspint Bit Host-to-CPU Interrupts Interrupts Between the Host and the CPUHint Bit CPU-to-Host Interrupts DSPINT=0CPU-to-Host Interrupt State Diagram Read Bursting FIFOs and BurstingWrite Bursting Fifo Flush Conditions Fifo Behavior When a Hardware Reset or Software Reset OccursSoftware Reset Considerations Emulation and Reset ConsiderationsHardware Reset Considerations Emulation ModesHPI Registers IntroductionHost Port Interface HPI Registers Soft Free R/W-0 R/W-0 Power and Emulation Management Register PwremumgmtBit Field Value Description SoftHost Port Interface Control Register Hpic Fetch DualhpiaFor host write cycle HPID/HPIC/HPIAR/HPIAWHost Port Interface Address Registers Hpiaw and Hpiar AddressBit Field Value Description 31-0 Data Register Hpid Field Descriptions Data Register HpidData HPI dataAppendix a Revision History TMS320C6457 HPI Revision HistorySeeAdditions/Modifications/Deletions Rfid Products Applications

TMS320C6457 specifications

The Texas Instruments TMS320C6457 is a high-performance digital signal processor (DSP) designed for demanding applications in telecommunications, industrial control, and video processing. As part of the TMS320C6000 family, the C6457 combines advanced features with impressive processing capabilities, making it a popular choice among developers looking for efficient and robust solutions.

One of the key features of the TMS320C6457 is its architecture, which is based on the super Harvard architecture. This design separates program and data memory paths, allowing for parallel instruction execution. The C6457 operates at clock speeds of up to 1 GHz, enabling it to deliver peak performance of over 6,000 MIPS (Million Instructions Per Second) and 12,000 MADDs (Multiply-Accumulate operations per second). Such high throughput makes the C6457 suitable for real-time processing applications that require rapid data handling.

The C6457 DSP integrates a rich set of on-chip resources, including up to 1MB of on-chip SRAM, which serves as a fast cache for data and instructions. The device features multiple high-speed interfaces, such as 10/100/1000 Ethernet, Serial RapidIO, and PCI-Express, facilitating seamless connectivity with other devices and systems. Furthermore, the TMS320C6457 supports various communication protocols, allowing it to adapt to a wide range of application scenarios.

In terms of power efficiency, the TMS320C6457 is designed with sophisticated power management features. It includes dynamic voltage and frequency scaling, which adjust power consumption based on workload requirements without compromising performance. This capability is particularly valuable in battery-operated devices or environments where thermal management is critical.

The TMS320C6457 also benefits from extensive software support, including the Texas Instruments DSP/BIOS real-time operating system and Code Composer Studio integrated development environment. Developers can leverage these tools for efficient code development, debugging, and system optimization. Additionally, Texas Instruments provides a range of libraries and algorithms optimized for the C6457, facilitating rapid application development.

Overall, the Texas Instruments TMS320C6457 DSP stands out due to its robust architecture, high processing capabilities, comprehensive connectivity options, and power management features. These attributes make it a versatile solution for a broad spectrum of applications in digital signal processing, where performance and efficiency are paramount. As technology continues to advance, the TMS320C6457 remains a relevant and potent option for developers seeking to push the boundaries of digital signal processing.
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