Texas Instruments TMS320C6457 manual Host Port Interface Address Registers Hpiaw and Hpiar

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HPI Registers

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8.4Host Port Interface Address Registers (HPIAW and HPIAR)

There are two 32-bit HPIA registers: HPIAW for write operations and HPIAR for read operations. The HPI can be configured such that HPIAW and HPIAR act as a single 32-bit HPIA (single-HPIA mode) or as two separate 32-bit HPIAs (dual-HPIA mode) from the perspective of the host. For details about these HPIA modes, see Section 2.

Figure 32 and Figure 33 show the format of an address register during host and CPU accesses. As shown in the figures, the host has full read/write access to the HPIAs, while the CPU can only read the HPIAs.

CAUTION

The host must always write a word address to the HPIAs. For example, L2 memory has a base byte address of 80 0000h that corresponds to a word address of 20 0000h. A host must write 20 0000h to the HPIA register to point the HPI to the base of L2 memory.

Figure 32. Format of an Address Register (HPIAW or HPIAR) - Host Access Permissions

31-0

ADDRESS

R/W-0

LEGEND: R = Read only; W = Write; -n= value after reset

Figure 33. Format of an Address Register (HPIAW or HPIAR) - CPU Access Permissions

31-0

ADDRESS

R-0

LEGEND: R = Read only; -n= value after reset

Table 9. Host Port Interface Address Registers (HPIAW or HPIAR) Field Descriptions

Bit

Field

Value

Description

 

 

 

 

31-0

ADDRESS

 

Read/write address. The host must initiate this field with a word address.

 

 

 

 

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Host Port Interface (HPI)

SPRUGK7A –March 2009 –Revised July 2010

Copyright © 2009–2010, Texas Instruments Incorporated

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Contents Users Guide SPRUGK7A -March 2009 -Revised July HDS2 HDS1 HCS Appendix aHas List of Figures List of Tables Notational Conventions About This ManualRelated Documentation From Texas Instruments Introduction to the HPI Summary of the HPI Registers HPI Signals Summary of the HPI SignalsSummary of HPI Registers HR/WI Hhwili Hasi HstrbSingle-HPIA Mode Using the Address RegistersDual-HPIA Mode Host-HPI Signal Connections HPI OperationHhwil HPI Configuration and Data Flow Available Host Data Strobe Pins Options for Connecting Host and HPI Data Strobe PinsHDS2, HDS1, and HCS Data Strobing and Chip Selection Access Types Selectable by the Hcntl Signals Cycle Types Selectable With the Hcntl and HR/W SignalsHCNTL10 and HR/W Indicating the Cycle Type Cycle TypeHas Forcing the HPI to Latch Control Information Early HCS Has Hrdy a HhwilHCS Has HR/W Hrdya HhwilPerforming a Multiplexed Access Without has Hstrb HR/WBit Multiplexed Mode Host Write Cycle With has Tied High Single-Halfword Hpic Cycle in the 16-Bit Multiplexed Mode Hardware Handshaking Using the HPI-Ready Hrdy SignalHrdy Behavior During 16-Bit Multiplexed Read Operations HrdyHrdy Behavior During 16-Bit Multiplexed Write Operations HR/W HhwilHrdy Behavior During 32-Bit Multiplexed Read Operations Hrdy Behavior During 32-Bit Multiplexed Write Operations Hpia WriteHpid Read Hpia Write HPID+ ReadsHpia Write Hpid Write Hpia Write HPID+ Writes Software Handshaking Using the HPI Ready Hrdy Bit Polling the Hrdy BitInterrupts Between the Host and the CPU Dspint Bit Host-to-CPU InterruptsHint Bit CPU-to-Host Interrupts DSPINT=0CPU-to-Host Interrupt State Diagram FIFOs and Bursting Read BurstingWrite Bursting Fifo Behavior When a Hardware Reset or Software Reset Occurs Fifo Flush ConditionsEmulation and Reset Considerations Software Reset ConsiderationsHardware Reset Considerations Emulation ModesIntroduction HPI RegistersHost Port Interface HPI Registers Power and Emulation Management Register Pwremumgmt Soft Free R/W-0 R/W-0Bit Field Value Description SoftHost Port Interface Control Register Hpic Dualhpia FetchFor host write cycle HPID/HPIC/HPIAR/HPIAWAddress Host Port Interface Address Registers Hpiaw and HpiarBit Field Value Description 31-0 Data Register Hpid Data Register Hpid Field DescriptionsData HPI dataTMS320C6457 HPI Revision History Appendix a Revision HistorySeeAdditions/Modifications/Deletions Products Applications Rfid

TMS320C6457 specifications

The Texas Instruments TMS320C6457 is a high-performance digital signal processor (DSP) designed for demanding applications in telecommunications, industrial control, and video processing. As part of the TMS320C6000 family, the C6457 combines advanced features with impressive processing capabilities, making it a popular choice among developers looking for efficient and robust solutions.

One of the key features of the TMS320C6457 is its architecture, which is based on the super Harvard architecture. This design separates program and data memory paths, allowing for parallel instruction execution. The C6457 operates at clock speeds of up to 1 GHz, enabling it to deliver peak performance of over 6,000 MIPS (Million Instructions Per Second) and 12,000 MADDs (Multiply-Accumulate operations per second). Such high throughput makes the C6457 suitable for real-time processing applications that require rapid data handling.

The C6457 DSP integrates a rich set of on-chip resources, including up to 1MB of on-chip SRAM, which serves as a fast cache for data and instructions. The device features multiple high-speed interfaces, such as 10/100/1000 Ethernet, Serial RapidIO, and PCI-Express, facilitating seamless connectivity with other devices and systems. Furthermore, the TMS320C6457 supports various communication protocols, allowing it to adapt to a wide range of application scenarios.

In terms of power efficiency, the TMS320C6457 is designed with sophisticated power management features. It includes dynamic voltage and frequency scaling, which adjust power consumption based on workload requirements without compromising performance. This capability is particularly valuable in battery-operated devices or environments where thermal management is critical.

The TMS320C6457 also benefits from extensive software support, including the Texas Instruments DSP/BIOS real-time operating system and Code Composer Studio integrated development environment. Developers can leverage these tools for efficient code development, debugging, and system optimization. Additionally, Texas Instruments provides a range of libraries and algorithms optimized for the C6457, facilitating rapid application development.

Overall, the Texas Instruments TMS320C6457 DSP stands out due to its robust architecture, high processing capabilities, comprehensive connectivity options, and power management features. These attributes make it a versatile solution for a broad spectrum of applications in digital signal processing, where performance and efficiency are paramount. As technology continues to advance, the TMS320C6457 remains a relevant and potent option for developers seeking to push the boundaries of digital signal processing.
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