Texas Instruments TMS320C6457 manual Software Handshaking Using the HPI Ready Hrdy Bit

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Software Handshaking Using the HPI Ready (HRDY) Bit

4Software Handshaking Using the HPI Ready (HRDY) Bit

In addition to the HRDY output signal, the HPI contains an HRDY bit in the control register (HPIC). This bit is useful for software polling when the host does not have an input pin to connect to the HRDY pin. In some cases, the host can read the HPIC register and, based on the status of the HRDY bit, determine whether the HPI is ready with read data (during a read cycle) or ready to latch write data (during a write cycle). Section 4.1 explains which read cycles and write cycles allow for polling of the HRDY bit.

NOTE: Software handshaking using the HRDY bit is not supported on all devices. See your device-specific data manual to determine if this functionality is supported on your device.

When the host is performing HPID host cycles with an automatic address increment between accesses, the value in the HRDY bit refers to the availability of space in the write FIFO or the availability of data in the read FIFO. If the previous host cycle was a read cycle, the HRDY bit refers to the read FIFO. If the previous host cycle was a write cycle, the HRDY bit refers to the write FIFO. If the previous host cycle set the FETCH bit of HPIC, the HRDY bit refers to the read FIFO. If the host has performed no data accesses yet, the HRDY bit refers to the write FIFO by default.

The HRDY bit reflects the level of an internal HRDY signal that is not gated by the chip select (HCS) input. The HRDY bit could be cleared in response to one of the following conditions:

•A prefetch was issued (FETCH = 1 in HPIC). HRDY is low until a flush occurs and new data is loaded in the read FIFO. When the data is available, the HRDY bit is set.

•The previous cycle was an autoincrement HPID write cycle, and the write FIFO became full. When space is available in the write FIFO, the HRDY bit is set.

•The previous cycle was a non-autoincrement HPID write cycle and the write FIFO is not empty. This condition indicates that the data has not yet been written to memory.

•The previous cycle was an HPID read cycle and the read FIFO is empty. Exception: If the previous cycle was a non-autoincrement HPID read cycle, when internal HSTRB becomes high (inactive), the HRDY bit stays 1 even though the FIFO is empty. This exception accommodates hosts that require the HPI to indicate that it is ready before the host begins the next cycle.

•The previous cycle was an HPID read cycle and a read FIFO flush is in progress.

4.1Polling the HRDY Bit

Read cycles. Only the FETCH command and autoincrement HPID read cycles may perform reads in this mode while using HRDY polling. Fixed address mode HPID read cycles may not be performed because during cycles in fixed address mode, the host must extend the read cycle until the read FIFO is flushed and the read data is retrieved from the DSP memory. Therefore, the host cannot create the HPIC cycles needed to poll HRDY because the host bus is busy with the current read access. The difference in a cycle with autoincrementing is that the host can release the host bus while the read data is automatically loaded into the read FIFO (due to the FETCH command and subsequent autoincrement read cycles).

Write cycles. As long as the HRDY bit is sampled high (and refers to write FIFO status), any type of write cycle may be performed by the host. This includes autoincrement HPID write cycles and fixed address mode HPID write cycle. It is possible to do either type of HPID cycle because the write data goes into the FIFO, and the internal transfer to DSP memory takes place after the host has ended the host bus cycle. This leaves the host bus inactive and available to the host for HPIC reads to poll the HRDY bit.

SPRUGK7A –March 2009 –Revised July 2010

Host Port Interface (HPI)

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Copyright © 2009–2010, Texas Instruments Incorporated

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Contents Users Guide SPRUGK7A -March 2009 -Revised July Has Appendix aHDS2 HDS1 HCS List of Figures List of Tables Related Documentation From Texas Instruments About This ManualNotational Conventions Introduction to the HPI Summary of the HPI Registers Summary of HPI Registers Summary of the HPI SignalsHPI Signals Hstrb HR/WI Hhwili HasiDual-HPIA Mode Using the Address RegistersSingle-HPIA Mode HPI Operation Host-HPI Signal ConnectionsHhwil HPI Configuration and Data Flow HDS2, HDS1, and HCS Data Strobing and Chip Selection Options for Connecting Host and HPI Data Strobe PinsAvailable Host Data Strobe Pins Cycle Types Selectable With the Hcntl and HR/W Signals Access Types Selectable by the Hcntl SignalsHCNTL10 and HR/W Indicating the Cycle Type Cycle TypeHas Forcing the HPI to Latch Control Information Early Hrdy a Hhwil HCS HasHrdya Hhwil HCS Has HR/WHstrb HR/W Performing a Multiplexed Access Without hasBit Multiplexed Mode Host Write Cycle With has Tied High Hardware Handshaking Using the HPI-Ready Hrdy Signal Single-Halfword Hpic Cycle in the 16-Bit Multiplexed ModeHrdy Hrdy Behavior During 16-Bit Multiplexed Read OperationsHR/W Hhwil Hrdy Behavior During 16-Bit Multiplexed Write OperationsHrdy Behavior During 32-Bit Multiplexed Read Operations Hpia Write Hrdy Behavior During 32-Bit Multiplexed Write OperationsHpid Read Hpia Write HPID+ ReadsHpia Write Hpid Write Hpia Write HPID+ Writes Polling the Hrdy Bit Software Handshaking Using the HPI Ready Hrdy BitDspint Bit Host-to-CPU Interrupts Interrupts Between the Host and the CPUHint Bit CPU-to-Host Interrupts DSPINT=0CPU-to-Host Interrupt State Diagram Read Bursting FIFOs and BurstingWrite Bursting Fifo Flush Conditions Fifo Behavior When a Hardware Reset or Software Reset OccursSoftware Reset Considerations Emulation and Reset ConsiderationsHardware Reset Considerations Emulation ModesHost Port Interface HPI Registers HPI RegistersIntroduction Soft Free R/W-0 R/W-0 Power and Emulation Management Register PwremumgmtBit Field Value Description SoftHost Port Interface Control Register Hpic Fetch DualhpiaFor host write cycle HPID/HPIC/HPIAR/HPIAWBit Field Value Description 31-0 Host Port Interface Address Registers Hpiaw and HpiarAddress Data Register Hpid Field Descriptions Data Register HpidData HPI dataSeeAdditions/Modifications/Deletions Appendix a Revision HistoryTMS320C6457 HPI Revision History Rfid Products Applications

TMS320C6457 specifications

The Texas Instruments TMS320C6457 is a high-performance digital signal processor (DSP) designed for demanding applications in telecommunications, industrial control, and video processing. As part of the TMS320C6000 family, the C6457 combines advanced features with impressive processing capabilities, making it a popular choice among developers looking for efficient and robust solutions.

One of the key features of the TMS320C6457 is its architecture, which is based on the super Harvard architecture. This design separates program and data memory paths, allowing for parallel instruction execution. The C6457 operates at clock speeds of up to 1 GHz, enabling it to deliver peak performance of over 6,000 MIPS (Million Instructions Per Second) and 12,000 MADDs (Multiply-Accumulate operations per second). Such high throughput makes the C6457 suitable for real-time processing applications that require rapid data handling.

The C6457 DSP integrates a rich set of on-chip resources, including up to 1MB of on-chip SRAM, which serves as a fast cache for data and instructions. The device features multiple high-speed interfaces, such as 10/100/1000 Ethernet, Serial RapidIO, and PCI-Express, facilitating seamless connectivity with other devices and systems. Furthermore, the TMS320C6457 supports various communication protocols, allowing it to adapt to a wide range of application scenarios.

In terms of power efficiency, the TMS320C6457 is designed with sophisticated power management features. It includes dynamic voltage and frequency scaling, which adjust power consumption based on workload requirements without compromising performance. This capability is particularly valuable in battery-operated devices or environments where thermal management is critical.

The TMS320C6457 also benefits from extensive software support, including the Texas Instruments DSP/BIOS real-time operating system and Code Composer Studio integrated development environment. Developers can leverage these tools for efficient code development, debugging, and system optimization. Additionally, Texas Instruments provides a range of libraries and algorithms optimized for the C6457, facilitating rapid application development.

Overall, the Texas Instruments TMS320C6457 DSP stands out due to its robust architecture, high processing capabilities, comprehensive connectivity options, and power management features. These attributes make it a versatile solution for a broad spectrum of applications in digital signal processing, where performance and efficiency are paramount. As technology continues to advance, the TMS320C6457 remains a relevant and potent option for developers seeking to push the boundaries of digital signal processing.
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