Texas Instruments TMS320C6457 manual Single-Halfword Hpic Cycle in the 16-Bit Multiplexed Mode

Page 22

HPI Operation

www.ti.com

3.8Single-Halfword HPIC Cycle in the 16-Bit Multiplexed Mode

In 16-bit multiplexed mode, the lower 16 bits of the HPIC registers are duplicated on the upper 16 bits during HPIC host accesses. Therefore, the host only needs to perform a single halfword cycle access to read the HPIC register. The host can drive the HHWIL pin either high or low, and either approach returns the same value. Figure 11 shows the special case in which the host performs a single-halfword cycle to access the HPIC (see Section 3.5). Although the example in Figure 11 has the HAS signal tied high, this type of HPIC cycle can also be done using the HAS signal to force early latching of control information.

Figure 11. 16-Bit Multiplexed Mode Single-Halfword HPIC Cycle with HAS Tied High

HCS

Internal

HSTRB

HR/W Valid

HCNTL[1:0] 00

HD[15:0]

Data 1

HRDY

HHWIL Valid

3.9Hardware Handshaking Using the HPI-Ready (HRDY) Signal

The HPI ready signal HRDY indicates to the host whether the HPI is ready to complete an access. During a read cycle, the HPI is ready (drives HRDY low) when it has data available for the host. During a write cycle, the HPI is ready (drives HRDY low) when it is ready to latch data from the host. If the HPI is not ready, it can drive HRDY high to insert wait states. These wait states indicate to the host that read data is not yet valid (read cycle) or that the HPI is not ready to latch write data (write cycle). The number of wait states that must be inserted by the HPI is dependent upon the state of the accessed resource. See the device-specific data manual for more information.

NOTE: In some cases, if the host does not have an input pin to connect to the HRDY pin, the host can check the readiness of the HPI by polling the HRDY bit in the control register (HPIC). For details, see Section 4.

When the HPI is not ready to complete the current cycle (HRDY high), the host can begin a new host cycle by forcing the HPI to latch new control information. However, once the cycle has been initiated, the host must wait until HRDY goes low before causing a rising edge on the internal strobe signal (internal HSTRB) to complete the cycle. If internal HSTRB goes high when the HPI is not ready, the cycle will be terminated with invalid data being returned (read cycle) or written (write cycle).

One reason the HPI may drive HRDY high is a not-ready condition in one of its first-in, first-out buffers (FIFOs). For example, any HPID access that occurs while the write FIFO is full or the read FIFO is empty may result in some number of wait states being inserted by the HPI. The FIFOs are explained in Section 6.

22

Host Port Interface (HPI)

SPRUGK7A –March 2009 –Revised July 2010

Copyright © 2009–2010, Texas Instruments Incorporated

Page 21 Page 23
Image 22
Page 21 Page 23
Contents Users Guide SPRUGK7A -March 2009 -Revised July HDS2 HDS1 HCS Appendix aHas List of Figures List of Tables Notational Conventions About This ManualRelated Documentation From Texas Instruments Introduction to the HPI Summary of the HPI Registers HPI Signals Summary of the HPI SignalsSummary of HPI Registers HR/WI Hhwili Hasi HstrbSingle-HPIA Mode Using the Address RegistersDual-HPIA Mode Host-HPI Signal Connections HPI OperationHhwil HPI Configuration and Data Flow Available Host Data Strobe Pins Options for Connecting Host and HPI Data Strobe PinsHDS2, HDS1, and HCS Data Strobing and Chip Selection HCNTL10 and HR/W Indicating the Cycle Type Access Types Selectable by the Hcntl SignalsCycle Types Selectable With the Hcntl and HR/W Signals Cycle TypeHas Forcing the HPI to Latch Control Information Early HCS Has Hrdy a HhwilHCS Has HR/W Hrdya HhwilPerforming a Multiplexed Access Without has Hstrb HR/WBit Multiplexed Mode Host Write Cycle With has Tied High Single-Halfword Hpic Cycle in the 16-Bit Multiplexed Mode Hardware Handshaking Using the HPI-Ready Hrdy SignalHrdy Behavior During 16-Bit Multiplexed Read Operations HrdyHrdy Behavior During 16-Bit Multiplexed Write Operations HR/W HhwilHrdy Behavior During 32-Bit Multiplexed Read Operations Hpid Read Hrdy Behavior During 32-Bit Multiplexed Write OperationsHpia Write Hpia Write HPID+ ReadsHpia Write Hpid Write Hpia Write HPID+ Writes Software Handshaking Using the HPI Ready Hrdy Bit Polling the Hrdy BitHint Bit CPU-to-Host Interrupts Interrupts Between the Host and the CPUDspint Bit Host-to-CPU Interrupts DSPINT=0CPU-to-Host Interrupt State Diagram FIFOs and Bursting Read BurstingWrite Bursting Fifo Behavior When a Hardware Reset or Software Reset Occurs Fifo Flush ConditionsHardware Reset Considerations Emulation and Reset ConsiderationsSoftware Reset Considerations Emulation ModesIntroduction HPI RegistersHost Port Interface HPI Registers Bit Field Value Description Power and Emulation Management Register PwremumgmtSoft Free R/W-0 R/W-0 SoftHost Port Interface Control Register Hpic For host write cycle DualhpiaFetch HPID/HPIC/HPIAR/HPIAWAddress Host Port Interface Address Registers Hpiaw and HpiarBit Field Value Description 31-0 Data Data Register HpidData Register Hpid Field Descriptions HPI dataTMS320C6457 HPI Revision History Appendix a Revision HistorySeeAdditions/Modifications/Deletions Products Applications Rfid

TMS320C6457 specifications

The Texas Instruments TMS320C6457 is a high-performance digital signal processor (DSP) designed for demanding applications in telecommunications, industrial control, and video processing. As part of the TMS320C6000 family, the C6457 combines advanced features with impressive processing capabilities, making it a popular choice among developers looking for efficient and robust solutions.

One of the key features of the TMS320C6457 is its architecture, which is based on the super Harvard architecture. This design separates program and data memory paths, allowing for parallel instruction execution. The C6457 operates at clock speeds of up to 1 GHz, enabling it to deliver peak performance of over 6,000 MIPS (Million Instructions Per Second) and 12,000 MADDs (Multiply-Accumulate operations per second). Such high throughput makes the C6457 suitable for real-time processing applications that require rapid data handling.

The C6457 DSP integrates a rich set of on-chip resources, including up to 1MB of on-chip SRAM, which serves as a fast cache for data and instructions. The device features multiple high-speed interfaces, such as 10/100/1000 Ethernet, Serial RapidIO, and PCI-Express, facilitating seamless connectivity with other devices and systems. Furthermore, the TMS320C6457 supports various communication protocols, allowing it to adapt to a wide range of application scenarios.

In terms of power efficiency, the TMS320C6457 is designed with sophisticated power management features. It includes dynamic voltage and frequency scaling, which adjust power consumption based on workload requirements without compromising performance. This capability is particularly valuable in battery-operated devices or environments where thermal management is critical.

The TMS320C6457 also benefits from extensive software support, including the Texas Instruments DSP/BIOS real-time operating system and Code Composer Studio integrated development environment. Developers can leverage these tools for efficient code development, debugging, and system optimization. Additionally, Texas Instruments provides a range of libraries and algorithms optimized for the C6457, facilitating rapid application development.

Overall, the Texas Instruments TMS320C6457 DSP stands out due to its robust architecture, high processing capabilities, comprehensive connectivity options, and power management features. These attributes make it a versatile solution for a broad spectrum of applications in digital signal processing, where performance and efficiency are paramount. As technology continues to advance, the TMS320C6457 remains a relevant and potent option for developers seeking to push the boundaries of digital signal processing.
Top Page Image Contents