Texas Instruments TMS320C6457 manual Using the Address Registers, Single-HPIA Mode, Dual-HPIA Mode

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Using the Address Registers

2Using the Address Registers

The HPI contains two 32-bit address registers: one for read operations (HPIAR) and one for write operations (HPIAW). These roles are unchanging from the position of the HPI DMA logic. HPI DMA logic collects the address from HPIAR when reading from DSP internal/external memory and collects the address from HPIAW when writing to DSP internal/external memory.

However, unlike the HPI DMA logic, the host can choose how to interact with the two HPIA registers. Using the DUALHPIA bit of HPIC, the host determines whether HPIAR and HPIAW act as a single 32-bit register (single-HPIA mode) or as two independent 32-bit registers (dual-HPIA mode).

CAUTION

The host must always write a word address to the HPIAs. For example, L2 memory has a base byte address of 80 0000h that corresponds to a word address of 20 0000h. A host must write 20 0000h to the HPIA register to point the HPI to the base of L2 memory.

2.1Single-HPIA Mode

If DUALHPIA = 0 in HPIC, HPIAR and HPIAW become a single HPIA register for the host. In this mode:

•A host HPIA write cycle (HCNTL[1:0] = 10b, HR/W = 0) updates HPIAR and HPIAW with the same value.

•Both HPIA registers are incremented during autoincrement read/write cycles (HCNTL[1:0] = 01b).

•An HPIA read cycle (HCNTL[1:0] = 10b, HR/W = 1) returns the contents of HPIAR, which should be identical to the contents of HPIAW.

To maintain consistency between the contents of HPIAR and HPIAW, the host should always re-initialize the HPIA registers after changing the state of the DUALHPIA bit. In addition, when DUALHPIA = 0, the host must always re-initialize the HPIA registers when it changes the data direction (from an HPID read cycle to an HPID write cycle, or vice versa). Otherwise, the memory location accessed by the HPI DMA logic might not be the host'sintended location.

2.2Dual-HPIA Mode

The host can take advantage of two independent HPIA registers by choosing the dual-HPIA mode (DUALHPIA = 1 in HPIC). In this mode:

•A host HPIA access (HCNTL[1:0] = 10b) reads/updates either HPIAR or HPIAW, depending on the value of the HPIA read/write select (HPIARWSEL) bit of HPIC. This bit is programmed by the host. While HPIARWSEL = 1, only HPIAR is read or updated by the host. While HPIARWSEL = 0, only HPIAW is read or updated by the host. The HPIARWSEL bit is only meaningful in the dual-HPIA mode.

NOTE: The HPIARWSEL bit does not affect the HPI DMA logic. Regardless of the value of HPIARWSEL, the HPI DMA logic uses HPIAR when reading from memory and HPIAW when writing to memory.

•A host HPID access with autoincrementing (HCNTL[1:0] = 01b) causes only the relevant HPIA value to be incremented to the next consecutive memory address. In an autoincrement read cycle, HPIAR is incremented after it has been used to perform the current read from memory. In an autoincrement write cycle, HPIAW is incremented after it has been used for the write operation.

SPRUGK7A –March 2009 –Revised July 2010

Host Port Interface (HPI)

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Copyright © 2009–2010, Texas Instruments Incorporated

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Contents Users Guide SPRUGK7A -March 2009 -Revised July Has Appendix aHDS2 HDS1 HCS List of Figures List of Tables Related Documentation From Texas Instruments About This ManualNotational Conventions Introduction to the HPI Summary of the HPI Registers Summary of HPI Registers Summary of the HPI SignalsHPI Signals Hstrb HR/WI Hhwili HasiDual-HPIA Mode Using the Address RegistersSingle-HPIA Mode HPI Operation Host-HPI Signal ConnectionsHhwil HPI Configuration and Data Flow HDS2, HDS1, and HCS Data Strobing and Chip Selection Options for Connecting Host and HPI Data Strobe PinsAvailable Host Data Strobe Pins Cycle Type Access Types Selectable by the Hcntl SignalsCycle Types Selectable With the Hcntl and HR/W Signals HCNTL10 and HR/W Indicating the Cycle TypeHas Forcing the HPI to Latch Control Information Early Hrdy a Hhwil HCS HasHrdya Hhwil HCS Has HR/WHstrb HR/W Performing a Multiplexed Access Without hasBit Multiplexed Mode Host Write Cycle With has Tied High Hardware Handshaking Using the HPI-Ready Hrdy Signal Single-Halfword Hpic Cycle in the 16-Bit Multiplexed ModeHrdy Hrdy Behavior During 16-Bit Multiplexed Read OperationsHR/W Hhwil Hrdy Behavior During 16-Bit Multiplexed Write OperationsHrdy Behavior During 32-Bit Multiplexed Read Operations Hpia Write HPID+ Reads Hrdy Behavior During 32-Bit Multiplexed Write OperationsHpia Write Hpid ReadHpia Write Hpid Write Hpia Write HPID+ Writes Polling the Hrdy Bit Software Handshaking Using the HPI Ready Hrdy BitDSPINT=0 Interrupts Between the Host and the CPUDspint Bit Host-to-CPU Interrupts Hint Bit CPU-to-Host InterruptsCPU-to-Host Interrupt State Diagram Read Bursting FIFOs and BurstingWrite Bursting Fifo Flush Conditions Fifo Behavior When a Hardware Reset or Software Reset OccursEmulation Modes Emulation and Reset ConsiderationsSoftware Reset Considerations Hardware Reset ConsiderationsHost Port Interface HPI Registers HPI RegistersIntroduction Soft Power and Emulation Management Register PwremumgmtSoft Free R/W-0 R/W-0 Bit Field Value DescriptionHost Port Interface Control Register Hpic HPID/HPIC/HPIAR/HPIAW DualhpiaFetch For host write cycleBit Field Value Description 31-0 Host Port Interface Address Registers Hpiaw and HpiarAddress HPI data Data Register HpidData Register Hpid Field Descriptions DataSeeAdditions/Modifications/Deletions Appendix a Revision HistoryTMS320C6457 HPI Revision History Rfid Products Applications

TMS320C6457 specifications

The Texas Instruments TMS320C6457 is a high-performance digital signal processor (DSP) designed for demanding applications in telecommunications, industrial control, and video processing. As part of the TMS320C6000 family, the C6457 combines advanced features with impressive processing capabilities, making it a popular choice among developers looking for efficient and robust solutions.

One of the key features of the TMS320C6457 is its architecture, which is based on the super Harvard architecture. This design separates program and data memory paths, allowing for parallel instruction execution. The C6457 operates at clock speeds of up to 1 GHz, enabling it to deliver peak performance of over 6,000 MIPS (Million Instructions Per Second) and 12,000 MADDs (Multiply-Accumulate operations per second). Such high throughput makes the C6457 suitable for real-time processing applications that require rapid data handling.

The C6457 DSP integrates a rich set of on-chip resources, including up to 1MB of on-chip SRAM, which serves as a fast cache for data and instructions. The device features multiple high-speed interfaces, such as 10/100/1000 Ethernet, Serial RapidIO, and PCI-Express, facilitating seamless connectivity with other devices and systems. Furthermore, the TMS320C6457 supports various communication protocols, allowing it to adapt to a wide range of application scenarios.

In terms of power efficiency, the TMS320C6457 is designed with sophisticated power management features. It includes dynamic voltage and frequency scaling, which adjust power consumption based on workload requirements without compromising performance. This capability is particularly valuable in battery-operated devices or environments where thermal management is critical.

The TMS320C6457 also benefits from extensive software support, including the Texas Instruments DSP/BIOS real-time operating system and Code Composer Studio integrated development environment. Developers can leverage these tools for efficient code development, debugging, and system optimization. Additionally, Texas Instruments provides a range of libraries and algorithms optimized for the C6457, facilitating rapid application development.

Overall, the Texas Instruments TMS320C6457 DSP stands out due to its robust architecture, high processing capabilities, comprehensive connectivity options, and power management features. These attributes make it a versatile solution for a broad spectrum of applications in digital signal processing, where performance and efficiency are paramount. As technology continues to advance, the TMS320C6457 remains a relevant and potent option for developers seeking to push the boundaries of digital signal processing.
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