Lantronix DSTni-EX manual

Page 95

Image 95

Contents Section Five DSTni-EX User GuidePage Master Distributor Copyright & TrademarkLantronix Technical SupportWarranty 3 I2C Controller Contents1 About This User Guide 2 SPI Controller5 CAN Controllers List of TablesTable 3-17. Clock Control Register List of Figures 1 About This User Guide Notes Notes are information requiring attention Intended AudienceConventions Navigating OnlineOrganization DSTni SPI Controller 2 SPI ControllerTheory of Operation SPI BackgroundTable 2-1. SPI Controller Register Summary SPI Controller Register SummaryTable 2-2. SPIDATA Register SPI Controller Register DefinitionsSPIDATA Register RESETWire-O CTL RegisterInterrupt Request Enable Phase SelectInterrupt Request SPISTAT RegisterTable 2-6. SPISTAT Register Table 2-7. SPISTAT Register DefinitionsTable 2-8. SPISSEL Register SPISSEL RegisterTable 2-10. BCNT Bit Settings SelectO SignalTable 2-12. DVDCNTRLO Register Definitions DVDCNTRLO RegisterDVDCNTRHI Table 2-11. DVDCNTRLO Register3 I2C Controller FeaturesFigure 3-1. DSTni I2C Controller Block Diagram Block DiagramI2C Background Master Transmit Mode I2C ControllerOperating Modes Microprocessor Response Table 3-1. Master Transmit Status CodesCode I2C StateTable 3-2. Codes After Servicing Interrupts Master Transmit Servicing the InterruptMaster Receive Mode Transmitting Each Data ByteTable 3-3. Status Codes After Each Data Byte Transmits All Bytes Transmit CompletelyTable 3-4. Master Receive Status Codes Table 3-5. Codes After Servicing Interrupt Master Receive Slave Transmit Mode Receiving Each Data ByteTable 3-6. Codes After Receiving Each Data Byte Slave Receive Mode Bus Arbitration Bus Clock ConsiderationsBus Clock Speed Clock SynchronizationTable 3-7. I 2C Controller Register Summary Programmer’s ReferenceI2C Controller Register Summary Resetting the I2C ControllerTable 3-8. Slave Address Register I2C Controller Register DefinitionsSlave Address Register General Call Address EnableTable 3-10. Data Register Data RegisterExtended Slave Address Control RegisterTable 3-12. Control Register Table 3-13. Control Register DefinitionsTable 3-14. Status Register Status RegisterStatus Code Table 3-15. Status Register DefinitionsTable 3-16. Status Codes Table 3-18. Clock Control Register Definitions Clock Control RegisterTable 3-17. Clock Control Register Table 3-22. Software Reset Register Definitions Software Reset RegisterExtended Slave Address Register Table 3-21. Software Reset Register4 USB Controller Serial Interface Engine USB BackgroundUSB Interrupt USB CoreBuffer Descriptor Table USB Hardware/Software InterfaceDigital Phase Lock Loop Logic Microprocessor InterfaceRx vs. Tx as a Target Device or Host Figure 4-1. Buffer Descriptor TableTable 4-3. 16-Bit USB Address Definitions Table 4-1. USB Data DirectionAddressing BDT Entries Table 4-2. 16-Bit USB AddressTable 4-5. USB Buffer Descriptor Format Table 4-4. BDT Data Used by USB Controller and MicroprocessorUSB Controller Determines… Microprocessor Determines…USB Ownership Table 4-6. USB Buffer Descriptor Format DefinitionsBD Owner DATA0/1 Transmit or ReceiveFigure 4-2. USB Token Transaction USB TransactionDedicated to host mode USB Register SummaryTable 4-7. USB Register Summary Table 4-9. 16- Interrupt Status Register Definitions USB Register DefinitionsInterrupt Status Register Table 4-8. Interrupt Status RegisterUSB Reset Enable/Disable USBRST InterruptSleep Timer Error ConditionTable 4-11. 16- Error Interrupt Status Register Definitions Error RegisterTable 4-10. Error Interrupt Status Register PID check field failed Error interrupt with two functionsData Field Received Not 8 Bits CRC16 FailureTable 4-13. Status Register Definitions Live USB Differential Receiver JSTATE SignalLive USB Single Ended Zero Signal Table 4-12. Status RegisterBDT PDD Reset USB Reset SignalHost Mode Enable valid for host mode only Resume SignalingTable 4-15. 16- Address Register Definitions Address RegisterTable 4-14. Address Register Frame Number Frame Number RegistersTable 4-16. Frame Number Register Table 4-17. Frame Number Register DefinitionsToken Register Table 4-20. Valid PID Tokens Endpoint for Token CommandTable 4-18. Token Register Table 4-19. Token Register DefinitionsTable 4-22. Endpoint Control Register Definitions Endpoint Control RegistersEndpoint Enable Table 4-21. Endpoint Control RegistersTable 4-23. Endpoint Control Register Definitions Host Mode OperationFigure 3. Enable Host Mode and Configure a Target Device Sample Host Mode OperationsFigure 4. Full-Speed Bulk Data Transfers to a Target Device Figure 4-5. Pull-up/Pull-down USB USB Pull-up/Pull-down ResistorsClock CLK USB Interface SignalsUSB Output Enable HOST Mode Enable5 CAN Controllers Data Exchanges and Communication Arbitration and Error CheckingCANBUS Background Table 5-1. Bit Rates for Different Cable Lengths CANBUS Speed and LengthRegister CAN Register SummariesRegister Summary Hex OffsetRegister Table 5-4. Detailed CAN Register Map Detailed CAN Register MapHex Offset Acceptance Filter Enable RegisterRegister Sending a Message CAN Register DefinitionsTX Message Registers Figure 5-1. TX Message RoutingTable 5-7. TxMessage0Data Tx Message RegistersTable 5-5. TxMessage0ID28 Table 5-6. TxMessage0ID12Message Data Table 5-12. TxMessage0Ctrl FlagsTable 5-13. TxMessage0 Register Definitions Message Identifier for Both Standard and Extended MessagesFigure 5-2. RX Message Routing RX Message RegistersTable 5-16. RxMessageID12 Rx Message RegistersTable 5-14. RxMessageID28 Table 5-15. Rx Message ID28 Register DefinitionsTable 5-23. Rx Message Data 23 Register Definitions Table 5-20. Rx Message DataTable 5-21. Rx Message Data 39 Register Definitions Table 5-22. Rx Message DataTable 5-29. Rx Message Msg Flags Register Definitions Table 5-26. RxMessage RTRTable 5-27. Rx Message RTR Register Definitions Table 5-28. Rx Message Msg FlagsTable 5-32. Error Status Error Count and Status RegistersTable 5-30. Tx/Rx Error Count Table 5-31. Tx\Rx Error Count Register Definitionstxlevel10 Table 5-34. Tx/Rx Message Level RegisterTable 5-35. Tx/Rx Message Level Register Definitions rxlevel10Format Error Interrupt FlagsNote The reset value of this register’s bits is indeterminate CRC ErrorBus Off State − int2n group error interrupts Interrupt Enable RegistersTable 5-38. Interrupt Enable Registers Table 5-39. Interrupt Enable Register DefinitionsOverload Condition − int3n group diagnostic interrupts CAN Operating ModeTable 5-40. Interrupt Enable Registers Table 5-41. Interrupt Enable Register DefinitionsTable 5-42. Bit Rate Divisor Register CAN Configuration RegistersConfiguration Bit Rate Figure 5-3. CAN Operating ModeCfgsjw Table 5-44. Configuration RegisterTable 5-45. Configuration Register Definitions Overwrite Last Messagetime quanta TQ Bit Timetseg1 + tseg2 +Table 5-48. Acceptance Mask 0 Register Acceptance Filter and Acceptance Code MaskTable 5-46. Acceptance Filter Enable Register Table 5-47. Acceptance Filter Enable Register DefinitionsD5556 Table 5-50. Acceptance Mask Register IDTable 5-51. Acceptance Mask Register ID12 Definitions Table 5-52. Acceptance Mask Register DataTable 5-57. Acceptance Mask Register ID12 Definitions Table 5-54. Acceptance Code RegisterTable 5-55. Acceptance Code Register Definitions Table 5-56. Acceptance Mask Register ID12Table 5-61. Arbitration Lost Capture Register Definitions CANbus AnalysisArbitration Lost Capture Register Table 5-60. Arbitration Lost Capture RegisterErrorcode Error Capture RegisterTable 5-62. Error Capture Register Table 5-63. Error Capture Register DefinitionsStuff Bit Inserted Table 5-65. Error Capture Register DefinitionsFrame Reference Register Table 5-64. Frame Reference RegisterFigure 5-5. CAN Bus Interface CAN Bus InterfaceInterface Connections Figure 5-6. CAN Connector+24V Figure 5-7. Power for CAN+5CAN GNDCAN0.01uf Figure 5-8. CAN Transceiver and Isolation Circuits