Bits | Field Name | Description |
2 | AAK | Acknowledge |
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| 1 = send Acknowledge (LOW level on SDA) during acknowledge clock pulse on |
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| the I2C bus if: |
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| −The entire |
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| address are received. |
|
| − The general call address is received and the GCE bit in the ADDR register is |
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| set to one. |
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| − A data byte is received in master or slave mode. |
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| 0 in slave transmitter mode = send Not Acknowledge (HIGH level on SDA) when |
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| a data byte is received in master or slave mode. After this byte transmits, the I2C |
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| controller enters state C8h and returns to idle state. The I2C controller does not |
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| respond as a slave unless AAK is set. |
1:0 | /// | Reserved |
Status Register
The Status register is a Read Only register that contains a
No relevant status information is available. No interrupt is generated.
The IFLG bit in the Control register is not set.
All other status codes correspond to a defined state of the I2C controller, as described in Table
When entering each of these states, the corresponding status code appears in this register and the IFLG bit in the Control register is set. When the IFLG bit clears, the status code returns to F8h
If an illegal condition occurs on the I2C bus, the bus enters the bus error state (status code 00h). To recover from this state, set the STP bit in the Control register and clear the IFLG bit. The I2C controller then returns to the idle state. No STOP condition transmits on the I2C bus.
Note: The STP and STA bits can be set to 1 at the same time to recover from the bus error, causing the I2C controller to send a START.
Table 3-14. Status Register
BIT | 7 | 6 |
| 5 |
| 4 |
| 3 |
| 2 |
| 1 |
| 0 |
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OFFSET |
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| D006 |
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| |
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| ||
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FIELD |
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| STATUS CODE |
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|
| /// |
| /// |
| /// |
| ||
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| ||||||
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RESET | 0 | 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
|
RW | R | R |
| R |
| R |
| R |
| R |
| R |
| R |
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