I2C Controller Register Definitions
Slave Address Register
Table 3-8. Slave Address Register
| BIT |
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| 7 |
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| 6 |
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| 5 |
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| 4 |
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| 3 |
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| 2 |
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| 1 |
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| 0 |
| |
| OFFSET |
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| D000 |
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| ||
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| EXTENDED |
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| Enable |
| |
| ADDRESS |
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| |
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| 1 |
|
| 1 |
|
| 1 |
| 1 |
| 0 |
|
| SLAX9 |
|
| SLAX8 |
|
| AddressCallGeneral |
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| FIELD |
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| SLA6 |
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| SLA5 |
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| SLA4 |
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| SLA3 |
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| SLA2 |
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| SLA1 |
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| SLA0 |
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| GCE |
| |
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| ||||
| RESET |
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| 0 |
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| 0 |
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| 0 |
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| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| |||||
| RW |
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| RW |
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| RW |
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| RW |
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| RW |
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| RW |
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| RW |
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| RW |
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| RW |
| |
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| Table |
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| Bits | Field Name |
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| Description |
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| 7:1 | SLA6 – SLA0 |
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| Slave Address |
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| For | ||||||||||||||||||||
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| mode. When the I2C controller receives this address after a START condition, it | ||||||||||||||||||||
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| generates an interrupt and enters slave mode. (SLA6 corresponds to the first bit | ||||||||||||||||||||
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| received from the I2C bus.) |
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| For | ||||||||||||||||||||
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| controller recognizes the correspondence to SLAX9 and SLAX8 of an extended | ||||||||||||||||||||
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| address, and sends an ACK. (The device does not generate an interrupt at this | ||||||||||||||||||||
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| point.) After receiving the next address byte, the I2C controller generates an | ||||||||||||||||||||
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| interrupt and enters slave mode. |
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| 0 | GCE |
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| General Call Address Enable |
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| 1 = I2C controller recognizes the | ||||||||||||||||||||
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| 0 = I2C controller does not recognize the | ||||||||||||||||||||
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| addressing). |
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