Lantronix DSTni-EX 12. Control Register, 13. Control Register Definitions, Start Condition

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Control Register

Table 3-12. Control Register

BIT

7

6

5

4

3

2

1

0

OFFSET

D004

FIELD

IEN

ENAB

STA

STP

IFLG

AAK

///

///

RESET

0

0

0

0

0

0

0

0

RW

RW

RW

RW

RW

RW

RW

RW

RW

		Table 3-13. Control Register Definitions

Bits	Field Name	Description
7	IEN	Extended Slave Address
		l = interrupt line (INTR) goes HIGH when the IFLG bit is set.
		0 = interrupt line remains LOW (default).
6	ENAB	Extended Slave Address
		1 = I2C Controller responds to calls to its slave address and to the general call
		address if the GCE bit in the ADDR register is set.
		0 = I2C bus inputs ISDA/ISCL are ignored and the I2C controller will not respond
		to any address on the bus (default).
5	STA	Start Condition
		1 = I2C controller enters master mode and transmits a START condition on the
		bus when the bus is free. If the I2C controller is already in master mode and one
		or more bytes have been transmitted, a repeated START condition is sent. If the
		I2C controller is being accessed in slave mode, the I2C controller completes the
		data transfer in slave mode and enters master mode when the bus is released.
		The STA bit is cleared automatically after a START condition has been sent.
		0 = no effect.
4	STP	Stop Condition
		1 and I2C controller is in slave mode in master mode = a stop condition is
		transmitted on the I2C bus.
		0 and I2C controller is in slave mode = I2C controller behaves as if a STOP
		condition has been received, but no STOP condition will be transmitted on the I2C
		bus. If both STA and STP bits are set, the I2C controller transmits the STOP
		condition (if in master mode), then transmits the START condition.
		0 = no effect.
		The STP bit is cleared automatically.
3	IFLG	I2C State
		1 = an I2C state has been entered. The only state that does not set IFLG is state
		F8h. See the Status register.
		1 and IEN bit is set = interrupt line goes HIGH. When IFLG is set by the I2C
		controller, the low period of the I2C bus clock line (SCL) is stretched and the data
		transfer is suspended.
		0 = interrupt line goes LOW and the I2C clock line is released.

25

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Contents Section Five DSTni-EX User GuidePage Lantronix Copyright & TrademarkTechnical Support Master DistributorWarranty 1 About This User Guide Contents2 SPI Controller 3 I2C Controller5 CAN Controllers List of TablesTable 3-17. Clock Control Register List of Figures 1 About This User Guide Conventions Intended AudienceNavigating Online Notes Notes are information requiring attentionOrganization Theory of Operation 2 SPI ControllerSPI Background DSTni SPI ControllerTable 2-1. SPI Controller Register Summary SPI Controller Register SummarySPIDATA Register SPI Controller Register DefinitionsRESET Table 2-2. SPIDATA RegisterInterrupt Request Enable CTL RegisterPhase Select Wire-OTable 2-6. SPISTAT Register SPISTAT RegisterTable 2-7. SPISTAT Register Definitions Interrupt RequestTable 2-10. BCNT Bit Settings SPISSEL RegisterSelectO Signal Table 2-8. SPISSEL RegisterDVDCNTRHI DVDCNTRLO RegisterTable 2-11. DVDCNTRLO Register Table 2-12. DVDCNTRLO Register Definitions3 I2C Controller FeaturesBlock Diagram I2C BackgroundFigure 3-1. DSTni I2C Controller Block Diagram I2C Controller Operating ModesMaster Transmit Mode Code Table 3-1. Master Transmit Status CodesI2C State Microprocessor ResponseTable 3-2. Codes After Servicing Interrupts Master Transmit Servicing the InterruptTable 3-3. Status Codes After Each Data Byte Transmits Transmitting Each Data ByteAll Bytes Transmit Completely Master Receive ModeTable 3-4. Master Receive Status Codes Table 3-5. Codes After Servicing Interrupt Master Receive Receiving Each Data Byte Table 3-6. Codes After Receiving Each Data ByteSlave Transmit Mode Slave Receive Mode Bus Clock Speed Bus Clock ConsiderationsClock Synchronization Bus Arbitration I2C Controller Register Summary Programmer’s Reference Resetting the I2C Controller Table 3-7. I 2C Controller Register SummarySlave Address Register I2C Controller Register DefinitionsGeneral Call Address Enable Table 3-8. Slave Address RegisterTable 3-10. Data Register Data RegisterTable 3-12. Control Register Control RegisterTable 3-13. Control Register Definitions Extended Slave AddressTable 3-14. Status Register Status RegisterTable 3-15. Status Register Definitions Table 3-16. Status CodesStatus Code Clock Control Register Table 3-17. Clock Control RegisterTable 3-18. Clock Control Register Definitions Extended Slave Address Register Software Reset RegisterTable 3-21. Software Reset Register Table 3-22. Software Reset Register Definitions4 USB Controller USB Interrupt USB BackgroundUSB Core Serial Interface EngineDigital Phase Lock Loop Logic USB Hardware/Software InterfaceMicroprocessor Interface Buffer Descriptor TableRx vs. Tx as a Target Device or Host Figure 4-1. Buffer Descriptor TableAddressing BDT Entries Table 4-1. USB Data DirectionTable 4-2. 16-Bit USB Address Table 4-3. 16-Bit USB Address DefinitionsUSB Controller Determines… Table 4-4. BDT Data Used by USB Controller and MicroprocessorMicroprocessor Determines… Table 4-5. USB Buffer Descriptor FormatBD Owner Table 4-6. USB Buffer Descriptor Format DefinitionsDATA0/1 Transmit or Receive USB OwnershipFigure 4-2. USB Token Transaction USB TransactionUSB Register Summary Table 4-7. USB Register SummaryDedicated to host mode Interrupt Status Register USB Register DefinitionsTable 4-8. Interrupt Status Register Table 4-9. 16- Interrupt Status Register DefinitionsSleep Timer Enable/Disable USBRST InterruptError Condition USB ResetError Register Table 4-10. Error Interrupt Status RegisterTable 4-11. 16- Error Interrupt Status Register Definitions Data Field Received Not 8 Bits Error interrupt with two functionsCRC16 Failure PID check field failedLive USB Single Ended Zero Signal Live USB Differential Receiver JSTATE SignalTable 4-12. Status Register Table 4-13. Status Register DefinitionsHost Mode Enable valid for host mode only USB Reset SignalResume Signaling BDT PDD ResetAddress Register Table 4-14. Address RegisterTable 4-15. 16- Address Register Definitions Table 4-16. Frame Number Register Frame Number RegistersTable 4-17. Frame Number Register Definitions Frame NumberToken Register Table 4-18. Token Register Endpoint for Token CommandTable 4-19. Token Register Definitions Table 4-20. Valid PID TokensEndpoint Enable Endpoint Control RegistersTable 4-21. Endpoint Control Registers Table 4-22. Endpoint Control Register DefinitionsTable 4-23. Endpoint Control Register Definitions Host Mode OperationFigure 3. Enable Host Mode and Configure a Target Device Sample Host Mode OperationsFigure 4. Full-Speed Bulk Data Transfers to a Target Device Figure 4-5. Pull-up/Pull-down USB USB Pull-up/Pull-down ResistorsUSB Output Enable USB Interface SignalsHOST Mode Enable Clock CLK5 CAN Controllers Arbitration and Error Checking CANBUS BackgroundData Exchanges and Communication Table 5-1. Bit Rates for Different Cable Lengths CANBUS Speed and LengthRegister Summary CAN Register SummariesHex Offset RegisterRegister Table 5-4. Detailed CAN Register Map Detailed CAN Register MapHex Offset Acceptance Filter Enable RegisterRegister TX Message Registers CAN Register DefinitionsFigure 5-1. TX Message Routing Sending a MessageTable 5-5. TxMessage0ID28 Tx Message RegistersTable 5-6. TxMessage0ID12 Table 5-7. TxMessage0DataTable 5-13. TxMessage0 Register Definitions Table 5-12. TxMessage0Ctrl FlagsMessage Identifier for Both Standard and Extended Messages Message DataFigure 5-2. RX Message Routing RX Message RegistersTable 5-14. RxMessageID28 Rx Message RegistersTable 5-15. Rx Message ID28 Register Definitions Table 5-16. RxMessageID12Table 5-21. Rx Message Data 39 Register Definitions Table 5-20. Rx Message DataTable 5-22. Rx Message Data Table 5-23. Rx Message Data 23 Register DefinitionsTable 5-27. Rx Message RTR Register Definitions Table 5-26. RxMessage RTRTable 5-28. Rx Message Msg Flags Table 5-29. Rx Message Msg Flags Register DefinitionsTable 5-30. Tx/Rx Error Count Error Count and Status RegistersTable 5-31. Tx\Rx Error Count Register Definitions Table 5-32. Error StatusTable 5-35. Tx/Rx Message Level Register Definitions Table 5-34. Tx/Rx Message Level Registerrxlevel10 txlevel10Note The reset value of this register’s bits is indeterminate Interrupt FlagsCRC Error Format ErrorTable 5-38. Interrupt Enable Registers Interrupt Enable RegistersTable 5-39. Interrupt Enable Register Definitions Bus Off State − int2n group error interruptsTable 5-40. Interrupt Enable Registers CAN Operating ModeTable 5-41. Interrupt Enable Register Definitions Overload Condition − int3n group diagnostic interruptsConfiguration Bit Rate CAN Configuration RegistersFigure 5-3. CAN Operating Mode Table 5-42. Bit Rate Divisor RegisterTable 5-45. Configuration Register Definitions Table 5-44. Configuration RegisterOverwrite Last Message Cfgsjwtseg1 + Bit Timetseg2 + time quanta TQTable 5-46. Acceptance Filter Enable Register Acceptance Filter and Acceptance Code MaskTable 5-47. Acceptance Filter Enable Register Definitions Table 5-48. Acceptance Mask 0 RegisterTable 5-51. Acceptance Mask Register ID12 Definitions Table 5-50. Acceptance Mask Register IDTable 5-52. Acceptance Mask Register Data D5556Table 5-55. Acceptance Code Register Definitions Table 5-54. Acceptance Code RegisterTable 5-56. Acceptance Mask Register ID12 Table 5-57. Acceptance Mask Register ID12 DefinitionsArbitration Lost Capture Register CANbus AnalysisTable 5-60. Arbitration Lost Capture Register Table 5-61. Arbitration Lost Capture Register DefinitionsTable 5-62. Error Capture Register Error Capture RegisterTable 5-63. Error Capture Register Definitions ErrorcodeFrame Reference Register Table 5-65. Error Capture Register DefinitionsTable 5-64. Frame Reference Register Stuff Bit InsertedInterface Connections CAN Bus InterfaceFigure 5-6. CAN Connector Figure 5-5. CAN Bus Interface+5CAN Figure 5-7. Power for CANGNDCAN +24V0.01uf Figure 5-8. CAN Transceiver and Isolation Circuits