Extended Slave Address Register
Table 3-19. Extended Slave Address Register
BIT |
| 7 |
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| 6 |
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| 5 |
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| 4 |
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| 3 |
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| 2 |
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| 1 |
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| 0 |
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OFFSET |
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| D008 |
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FIELD |
| SLAX7 |
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| SLAX6 |
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| SLAX5 |
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| SLAX4 |
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| SLAX3 |
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| SLAX2 |
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| SLAX1 |
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| SLAX0 |
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RESET |
| 0 |
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| 0 |
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| 0 |
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| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
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RW |
| RW |
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| RW |
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| RW |
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| RW |
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| RW |
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| RW |
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| RW |
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| RW |
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Table 3-20. Extended Slave Address Register Definitions
Bits | Field Name | Description |
7 | SLAX7 | Extended slave address. |
6 | SLAX6 | Extended slave address. |
5 | SLAX5 | Extended slave address. |
4 | SLAX4 | Extended slave address. |
3 | SLAX3 | Extended slave address. |
2 | SLAX2 | Extended slave address. |
1 | SLAX1 | Extended slave address. |
0 | SLAX0 | Extended slave address. |
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Software Reset Register
Table 3-21. Software Reset Register
BIT |
| 7 |
| 6 | 5 | 4 |
| 3 |
| 2 | 1 | 0 |
OFFSET |
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| D00E |
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FIELD |
| HRST |
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| /// |
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RESET |
| 0 |
| 0 | 0 | 0 |
| 0 |
| 0 | 0 | 0 |
RW |
| RW |
| RW | RW | RW |
| RW |
| RW | RW | RW |
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| Table | |
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Bits | Field Name |
| Description |
7 | HRST |
| Hardware Reset to I2C Controller |
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| 1 = causes the I2C controller to reset the same as a hardware reset. The |
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| hardware reset is |
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| 0 = only the I2C controller Control register is cleared. |
6:0 | /// |
| Reserved |
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