Lantronix DSTni-EX manual 1. Master Transmit Status Codes, I2C State, Microprocessor Response

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	Table 3-1. Master Transmit Status Codes

Code	I2C State		Microprocessor Response	Next I2C Action
18h	Addr + W transmitted,		7-bit address:
	ACK received		Write byte to DATA, clear IFLG	Transmit data byte, receive
			OR	ACK
			OR
			Set STA, clear IFLG	Transmit repeated START
			OR
			Set STP, clear IFLG	Transmit STOP
			OR
			Set STA & STP, clear IFLG	Transmit STOP, then START
			10-bit address:
			Write extended address byte to	Transmit extended address byte
			DATA, clear IFLG
20h	Addr + W transmitted,		Same as code 18h	Same as code 18h
	ACK not received
38h	Arbitration lost		Clear IFLG	Return to idle
			OR
			Set STA, clearIFLG	Transmit START when bus is free
68h	Arbitration lost,		Clear IFLG, AAK=0	Receive data byte, transmit not ACK
	SLA + W received,
	ACK transmitted		OR
			Clear IFLG, AAK=1	Receive data byte, transmit ACK
78h	Arbitration lost,		Same as code 68h	Same as code 68h
	general call addr
	received, ACK
	transmitted
B0h	Arbitration lost, SLA + R		Write byte to DATA, clear IFLG,	Transmit last byte, receive ACK
	received, ACK		AAK=0
	transmitted		OR
			OR
			Write byte to DATA, clear IFLG,	Transmit data byte, receive ACK
			AAK=1

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Contents DSTni-EX User Guide Section FivePage Technical Support Copyright & TrademarkLantronix Master DistributorWarranty 2 SPI Controller Contents1 About This User Guide 3 I2C ControllerList of Tables 5 CAN ControllersTable 3-17. Clock Control Register List of Figures 1 About This User Guide Navigating Online Intended AudienceConventions Notes Notes are information requiring attentionOrganization SPI Background 2 SPI ControllerTheory of Operation DSTni SPI ControllerSPI Controller Register Summary Table 2-1. SPI Controller Register SummaryRESET SPI Controller Register DefinitionsSPIDATA Register Table 2-2. SPIDATA RegisterPhase Select CTL RegisterInterrupt Request Enable Wire-OTable 2-7. SPISTAT Register Definitions SPISTAT RegisterTable 2-6. SPISTAT Register Interrupt RequestSelectO Signal SPISSEL RegisterTable 2-10. BCNT Bit Settings Table 2-8. SPISSEL RegisterTable 2-11. DVDCNTRLO Register DVDCNTRLO RegisterDVDCNTRHI Table 2-12. DVDCNTRLO Register DefinitionsFeatures 3 I2C ControllerI2C Background Block DiagramFigure 3-1. DSTni I2C Controller Block Diagram Operating Modes I2C ControllerMaster Transmit Mode I2C State Table 3-1. Master Transmit Status CodesCode Microprocessor ResponseServicing the Interrupt Table 3-2. Codes After Servicing Interrupts Master TransmitAll Bytes Transmit Completely Transmitting Each Data ByteTable 3-3. Status Codes After Each Data Byte Transmits Master Receive ModeTable 3-4. Master Receive Status Codes Table 3-5. Codes After Servicing Interrupt Master Receive Table 3-6. Codes After Receiving Each Data Byte Receiving Each Data ByteSlave Transmit Mode Slave Receive Mode Clock Synchronization Bus Clock ConsiderationsBus Clock Speed Bus ArbitrationResetting the I2C Controller Programmer’s ReferenceI2C Controller Register Summary Table 3-7. I 2C Controller Register SummaryGeneral Call Address Enable I2C Controller Register DefinitionsSlave Address Register Table 3-8. Slave Address RegisterData Register Table 3-10. Data RegisterTable 3-13. Control Register Definitions Control RegisterTable 3-12. Control Register Extended Slave AddressStatus Register Table 3-14. Status RegisterTable 3-16. Status Codes Table 3-15. Status Register DefinitionsStatus Code Table 3-17. Clock Control Register Clock Control RegisterTable 3-18. Clock Control Register Definitions Table 3-21. Software Reset Register Software Reset RegisterExtended Slave Address Register Table 3-22. Software Reset Register Definitions4 USB Controller USB Core USB BackgroundUSB Interrupt Serial Interface EngineMicroprocessor Interface USB Hardware/Software InterfaceDigital Phase Lock Loop Logic Buffer Descriptor TableFigure 4-1. Buffer Descriptor Table Rx vs. Tx as a Target Device or HostTable 4-2. 16-Bit USB Address Table 4-1. USB Data DirectionAddressing BDT Entries Table 4-3. 16-Bit USB Address DefinitionsMicroprocessor Determines… Table 4-4. BDT Data Used by USB Controller and MicroprocessorUSB Controller Determines… Table 4-5. USB Buffer Descriptor FormatDATA0/1 Transmit or Receive Table 4-6. USB Buffer Descriptor Format DefinitionsBD Owner USB OwnershipUSB Transaction Figure 4-2. USB Token TransactionTable 4-7. USB Register Summary USB Register SummaryDedicated to host mode Table 4-8. Interrupt Status Register USB Register DefinitionsInterrupt Status Register Table 4-9. 16- Interrupt Status Register DefinitionsError Condition Enable/Disable USBRST InterruptSleep Timer USB ResetTable 4-10. Error Interrupt Status Register Error RegisterTable 4-11. 16- Error Interrupt Status Register Definitions CRC16 Failure Error interrupt with two functionsData Field Received Not 8 Bits PID check field failedTable 4-12. Status Register Live USB Differential Receiver JSTATE SignalLive USB Single Ended Zero Signal Table 4-13. Status Register DefinitionsResume Signaling USB Reset SignalHost Mode Enable valid for host mode only BDT PDD ResetTable 4-14. Address Register Address RegisterTable 4-15. 16- Address Register Definitions Table 4-17. Frame Number Register Definitions Frame Number RegistersTable 4-16. Frame Number Register Frame NumberToken Register Table 4-19. Token Register Definitions Endpoint for Token CommandTable 4-18. Token Register Table 4-20. Valid PID TokensTable 4-21. Endpoint Control Registers Endpoint Control RegistersEndpoint Enable Table 4-22. Endpoint Control Register DefinitionsHost Mode Operation Table 4-23. Endpoint Control Register DefinitionsSample Host Mode Operations Figure 3. Enable Host Mode and Configure a Target DeviceFigure 4. Full-Speed Bulk Data Transfers to a Target Device USB Pull-up/Pull-down Resistors Figure 4-5. Pull-up/Pull-down USBHOST Mode Enable USB Interface SignalsUSB Output Enable Clock CLK5 CAN Controllers CANBUS Background Arbitration and Error CheckingData Exchanges and Communication CANBUS Speed and Length Table 5-1. Bit Rates for Different Cable LengthsHex Offset CAN Register SummariesRegister Summary RegisterHex Offset Detailed CAN Register Map Table 5-4. Detailed CAN Register MapAcceptance Filter Enable Register Hex OffsetRegister Figure 5-1. TX Message Routing CAN Register DefinitionsTX Message Registers Sending a MessageTable 5-6. TxMessage0ID12 Tx Message RegistersTable 5-5. TxMessage0ID28 Table 5-7. TxMessage0DataMessage Identifier for Both Standard and Extended Messages Table 5-12. TxMessage0Ctrl FlagsTable 5-13. TxMessage0 Register Definitions Message DataRX Message Registers Figure 5-2. RX Message RoutingTable 5-15. Rx Message ID28 Register Definitions Rx Message RegistersTable 5-14. RxMessageID28 Table 5-16. RxMessageID12Table 5-22. Rx Message Data Table 5-20. Rx Message DataTable 5-21. Rx Message Data 39 Register Definitions Table 5-23. Rx Message Data 23 Register DefinitionsTable 5-28. Rx Message Msg Flags Table 5-26. RxMessage RTRTable 5-27. Rx Message RTR Register Definitions Table 5-29. Rx Message Msg Flags Register DefinitionsTable 5-31. Tx\Rx Error Count Register Definitions Error Count and Status RegistersTable 5-30. Tx/Rx Error Count Table 5-32. Error Statusrxlevel10 Table 5-34. Tx/Rx Message Level RegisterTable 5-35. Tx/Rx Message Level Register Definitions txlevel10CRC Error Interrupt FlagsNote The reset value of this register’s bits is indeterminate Format ErrorTable 5-39. Interrupt Enable Register Definitions Interrupt Enable RegistersTable 5-38. Interrupt Enable Registers Bus Off State − int2n group error interruptsTable 5-41. Interrupt Enable Register Definitions CAN Operating ModeTable 5-40. Interrupt Enable Registers Overload Condition − int3n group diagnostic interruptsFigure 5-3. CAN Operating Mode CAN Configuration RegistersConfiguration Bit Rate Table 5-42. Bit Rate Divisor RegisterOverwrite Last Message Table 5-44. Configuration RegisterTable 5-45. Configuration Register Definitions Cfgsjwtseg2 + Bit Timetseg1 + time quanta TQTable 5-47. Acceptance Filter Enable Register Definitions Acceptance Filter and Acceptance Code MaskTable 5-46. Acceptance Filter Enable Register Table 5-48. Acceptance Mask 0 RegisterTable 5-52. Acceptance Mask Register Data Table 5-50. Acceptance Mask Register IDTable 5-51. Acceptance Mask Register ID12 Definitions D5556Table 5-56. Acceptance Mask Register ID12 Table 5-54. Acceptance Code RegisterTable 5-55. Acceptance Code Register Definitions Table 5-57. Acceptance Mask Register ID12 DefinitionsTable 5-60. Arbitration Lost Capture Register CANbus AnalysisArbitration Lost Capture Register Table 5-61. Arbitration Lost Capture Register DefinitionsTable 5-63. Error Capture Register Definitions Error Capture RegisterTable 5-62. Error Capture Register ErrorcodeTable 5-64. Frame Reference Register Table 5-65. Error Capture Register DefinitionsFrame Reference Register Stuff Bit InsertedFigure 5-6. CAN Connector CAN Bus InterfaceInterface Connections Figure 5-5. CAN Bus InterfaceGNDCAN Figure 5-7. Power for CAN+5CAN +24VFigure 5-8. CAN Transceiver and Isolation Circuits 0.01uf