Lantronix DSTni-EX USB Reset Signal, Host Mode Enable valid for host mode only, Resume Signaling

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Bits	Field Name	Description
12	RESET	USB Reset Signal
		1	= enables the USB to generate USB reset signaling. This allows the USB to
		reset USB peripherals. This control signal is only valid in host mode, (i.e.,
		HOST_MDOE_EN=1). Software must set RESET to 1 for the required amount of
		time and then clear it to 0 to end reset signaling. For more information about
		RESET signaling, see Section 7.1.4.3 of the USB specification version 1.0.
11	HOSTMODE EN	Host Mode Enable (valid for host mode only)
		1	= enables the USB to operate in host mode. In host mode, the USB performs
		USB transactions under the programmed control of the host processor.
		0	= USB not enabled for host mode.
10	RESUME	Resume Signaling
		1	= allows the USB to execute resume signaling. This lets the USB perform
		remote wake-up. Software must set RESUME to 1 for the required amount of time
		and then clear it to 0. If the HOST_MODE_EN bit is set, the USB appends a Low
		Speed End-of -packet to the Resume signaling when the RESUME bit is cleared.
		For more information about RESUME signaling, see Section 7.1.4.5 of the USB
		specification version 1.0.
		0	= prevents the USB from executing resume signaling.
9	ODD_RST	BDT PDD Reset
		1	= resets all the BDT ODD ping/pong bits to 0, which then specifies the EVEN
		BDT bank.
		0	= does not reset the BDT ODD ping/pong bits.
8	USB_EN	USB Enable
		1	= enables the USB to operate, clearing it will disable the USB. It causes the SIE
		to reset all of its ODD bits to the BDTs. Therefore, setting this bit resets much of
		the logic in the SIE. When host mode is enabled clearing this bit causes the SIE
		to stop sending SOF tokens.
7:4	ENDP	Encode Endpoint
		Encode the endpoint address receiving or transmitting the previous token. This
		lets the microprocessor determine which BDT entry is updated by the last USB
		transaction. These four bits correspond to the endpoint address 3:0, respectively.
3	TX	Last Transaction Transmit/Receive
		1	= last BDT updated is a transmit (TX) transfer.
		0	= last transaction is a receive (RX) data transfer.
2	ODD	ODD Bank of BDT
		Last buffer descriptor updated is in the odd bank of the BDT.
1:0	///	Reserved

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Contents DSTni-EX User Guide Section FivePage Copyright & Trademark LantronixTechnical Support Master DistributorWarranty Contents 1 About This User Guide2 SPI Controller 3 I2C ControllerList of Tables 5 CAN ControllersTable 3-17. Clock Control Register List of Figures 1 About This User Guide Intended Audience ConventionsNavigating Online Notes Notes are information requiring attentionOrganization 2 SPI Controller Theory of OperationSPI Background DSTni SPI ControllerSPI Controller Register Summary Table 2-1. SPI Controller Register SummarySPI Controller Register Definitions SPIDATA RegisterRESET Table 2-2. SPIDATA RegisterCTL Register Interrupt Request EnablePhase Select Wire-OSPISTAT Register Table 2-6. SPISTAT RegisterTable 2-7. SPISTAT Register Definitions Interrupt RequestSPISSEL Register Table 2-10. BCNT Bit SettingsSelectO Signal Table 2-8. SPISSEL RegisterDVDCNTRLO Register DVDCNTRHITable 2-11. DVDCNTRLO Register Table 2-12. DVDCNTRLO Register DefinitionsFeatures 3 I2C ControllerI2C Background Block DiagramFigure 3-1. DSTni I2C Controller Block Diagram Operating Modes I2C ControllerMaster Transmit Mode Table 3-1. Master Transmit Status Codes CodeI2C State Microprocessor ResponseServicing the Interrupt Table 3-2. Codes After Servicing Interrupts Master TransmitTransmitting Each Data Byte Table 3-3. Status Codes After Each Data Byte TransmitsAll Bytes Transmit Completely Master Receive ModeTable 3-4. Master Receive Status Codes Table 3-5. Codes After Servicing Interrupt Master Receive Table 3-6. Codes After Receiving Each Data Byte Receiving Each Data ByteSlave Transmit Mode Slave Receive Mode Bus Clock Considerations Bus Clock SpeedClock Synchronization Bus ArbitrationProgrammer’s Reference I2C Controller Register SummaryResetting the I2C Controller Table 3-7. I 2C Controller Register SummaryI2C Controller Register Definitions Slave Address RegisterGeneral Call Address Enable Table 3-8. Slave Address RegisterData Register Table 3-10. Data RegisterControl Register Table 3-12. Control RegisterTable 3-13. Control Register Definitions Extended Slave AddressStatus Register Table 3-14. Status RegisterTable 3-16. Status Codes Table 3-15. Status Register DefinitionsStatus Code Table 3-17. Clock Control Register Clock Control RegisterTable 3-18. Clock Control Register Definitions Software Reset Register Extended Slave Address RegisterTable 3-21. Software Reset Register Table 3-22. Software Reset Register Definitions4 USB Controller USB Background USB InterruptUSB Core Serial Interface EngineUSB Hardware/Software Interface Digital Phase Lock Loop LogicMicroprocessor Interface Buffer Descriptor TableFigure 4-1. Buffer Descriptor Table Rx vs. Tx as a Target Device or HostTable 4-1. USB Data Direction Addressing BDT EntriesTable 4-2. 16-Bit USB Address Table 4-3. 16-Bit USB Address DefinitionsTable 4-4. BDT Data Used by USB Controller and Microprocessor USB Controller Determines…Microprocessor Determines… Table 4-5. USB Buffer Descriptor FormatTable 4-6. USB Buffer Descriptor Format Definitions BD OwnerDATA0/1 Transmit or Receive USB OwnershipUSB Transaction Figure 4-2. USB Token TransactionTable 4-7. USB Register Summary USB Register SummaryDedicated to host mode USB Register Definitions Interrupt Status RegisterTable 4-8. Interrupt Status Register Table 4-9. 16- Interrupt Status Register DefinitionsEnable/Disable USBRST Interrupt Sleep TimerError Condition USB ResetTable 4-10. Error Interrupt Status Register Error RegisterTable 4-11. 16- Error Interrupt Status Register Definitions Error interrupt with two functions Data Field Received Not 8 BitsCRC16 Failure PID check field failedLive USB Differential Receiver JSTATE Signal Live USB Single Ended Zero SignalTable 4-12. Status Register Table 4-13. Status Register DefinitionsUSB Reset Signal Host Mode Enable valid for host mode onlyResume Signaling BDT PDD ResetTable 4-14. Address Register Address RegisterTable 4-15. 16- Address Register Definitions Frame Number Registers Table 4-16. Frame Number RegisterTable 4-17. Frame Number Register Definitions Frame NumberToken Register Endpoint for Token Command Table 4-18. Token RegisterTable 4-19. Token Register Definitions Table 4-20. Valid PID TokensEndpoint Control Registers Endpoint EnableTable 4-21. Endpoint Control Registers Table 4-22. Endpoint Control Register DefinitionsHost Mode Operation Table 4-23. Endpoint Control Register DefinitionsSample Host Mode Operations Figure 3. Enable Host Mode and Configure a Target DeviceFigure 4. Full-Speed Bulk Data Transfers to a Target Device USB Pull-up/Pull-down Resistors Figure 4-5. Pull-up/Pull-down USBUSB Interface Signals USB Output EnableHOST Mode Enable Clock CLK5 CAN Controllers CANBUS Background Arbitration and Error CheckingData Exchanges and Communication CANBUS Speed and Length Table 5-1. Bit Rates for Different Cable LengthsCAN Register Summaries Register SummaryHex Offset RegisterHex Offset Detailed CAN Register Map Table 5-4. Detailed CAN Register MapAcceptance Filter Enable Register Hex OffsetRegister CAN Register Definitions TX Message RegistersFigure 5-1. TX Message Routing Sending a MessageTx Message Registers Table 5-5. TxMessage0ID28Table 5-6. TxMessage0ID12 Table 5-7. TxMessage0DataTable 5-12. TxMessage0Ctrl Flags Table 5-13. TxMessage0 Register DefinitionsMessage Identifier for Both Standard and Extended Messages Message DataRX Message Registers Figure 5-2. RX Message RoutingRx Message Registers Table 5-14. RxMessageID28Table 5-15. Rx Message ID28 Register Definitions Table 5-16. RxMessageID12Table 5-20. Rx Message Data Table 5-21. Rx Message Data 39 Register DefinitionsTable 5-22. Rx Message Data Table 5-23. Rx Message Data 23 Register DefinitionsTable 5-26. RxMessage RTR Table 5-27. Rx Message RTR Register DefinitionsTable 5-28. Rx Message Msg Flags Table 5-29. Rx Message Msg Flags Register DefinitionsError Count and Status Registers Table 5-30. Tx/Rx Error CountTable 5-31. Tx\Rx Error Count Register Definitions Table 5-32. Error StatusTable 5-34. Tx/Rx Message Level Register Table 5-35. Tx/Rx Message Level Register Definitionsrxlevel10 txlevel10Interrupt Flags Note The reset value of this register’s bits is indeterminateCRC Error Format ErrorInterrupt Enable Registers Table 5-38. Interrupt Enable RegistersTable 5-39. Interrupt Enable Register Definitions Bus Off State − int2n group error interruptsCAN Operating Mode Table 5-40. Interrupt Enable RegistersTable 5-41. Interrupt Enable Register Definitions Overload Condition − int3n group diagnostic interruptsCAN Configuration Registers Configuration Bit RateFigure 5-3. CAN Operating Mode Table 5-42. Bit Rate Divisor RegisterTable 5-44. Configuration Register Table 5-45. Configuration Register DefinitionsOverwrite Last Message CfgsjwBit Time tseg1 +tseg2 + time quanta TQAcceptance Filter and Acceptance Code Mask Table 5-46. Acceptance Filter Enable RegisterTable 5-47. Acceptance Filter Enable Register Definitions Table 5-48. Acceptance Mask 0 RegisterTable 5-50. Acceptance Mask Register ID Table 5-51. Acceptance Mask Register ID12 DefinitionsTable 5-52. Acceptance Mask Register Data D5556Table 5-54. Acceptance Code Register Table 5-55. Acceptance Code Register DefinitionsTable 5-56. Acceptance Mask Register ID12 Table 5-57. Acceptance Mask Register ID12 DefinitionsCANbus Analysis Arbitration Lost Capture RegisterTable 5-60. Arbitration Lost Capture Register Table 5-61. Arbitration Lost Capture Register DefinitionsError Capture Register Table 5-62. Error Capture RegisterTable 5-63. Error Capture Register Definitions ErrorcodeTable 5-65. Error Capture Register Definitions Frame Reference RegisterTable 5-64. Frame Reference Register Stuff Bit InsertedCAN Bus Interface Interface ConnectionsFigure 5-6. CAN Connector Figure 5-5. CAN Bus InterfaceFigure 5-7. Power for CAN +5CANGNDCAN +24VFigure 5-8. CAN Transceiver and Isolation Circuits 0.01uf