Table 5-26. RxMessage: RTR
BIT | 15 | 14 |
| 13 |
| 12 |
| 11 | 10 | 9 | 8 | 7 |
| 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OFFSET |
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| 3C |
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FIELD |
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| AFI_2 | AFI_1 | AFI_0 | /// |
| RTR | IDE | DLC_3 | DLC_2 | DLC_1 | DLC_0 | ||
RESET | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
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R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | |||
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| Table | |
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| Bits | Field Name | Description |
| 15:11 | /// | Reserved |
| 10:8 | AFI[2:0] | Acceptance Filter Indicator |
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| Indicates which acceptance filter(s) accepted the incoming message. If |
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| more than one filter accepted the message, more than one bit is set. |
| 7:6 | /// | Reserved |
| 5 | RTR | Remote Bit |
| 4 | IDE | Extended Identifier Bit |
| 3 | DLC[3:0] | Data Length Code |
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| Invalid values are transmitted as they are. |
Table 5-28. Rx Message: Msg Flags
BIT | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OFFSET |
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| 3E |
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FIELD |
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| Rx Fifo2 | Rx Fifo0 |
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| Msg Aval | |
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RESET | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R | R | R | R/W | R/W | R/W | R/W | R/W |
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| Bits | Field Name | Description |
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| 15:8 | /// | Reserved |
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| 7:5 | Rx_Fifo[2:0]: | Rx FIFO Status |
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| These two Read Only flags indicate how many messages are |
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| waiting in the queue. |
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| 000 | = empty |
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| 001 | = 1/4 full |
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| 010 | = 1/2 full |
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| 011 | = 3/4 full |
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| 100 | = full |
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| Other values are not applicable. |
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| 4:1 | /// | Reserved |
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| 0 | Msg Avail | Message Available |
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| MsgAval goes HIGH when a new message is available. Writing a ‘ 1’ clears |
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| this flag and indicates that the message has been read. If another message |
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| is available, this flag is not cleared and the new message from RxMsg1 |
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| buffer is accessible. |
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| 69 |
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