Lantronix DSTni-EX CAN Register Summaries, Register Summary, Hex Offset, Theory of Operation

Page 66

Theory of Operation

The CAN controller appears to the microprocessor as an I/O device. Each peripheral has 256 bytes of I/O address space allocated to it. CAN0 and CAN1 share Interrupt 6.

Table 5-2. CAN I/O Address

CAN Controller

Base Address

CAN0

A800h

CAN1

A900h

CAN Register Summaries

DSTni contains two independent CAN channels. Operation and access to each device, however, is the same. The only difference is the starting I/O base address for each channel, as shown in Table 5-2.

Both CAN channels have their registers located and fixed in the internal I/O space of the DSTni chip. Both are implemented as true 16-bit devices. Therefore, all accesses made to the CAN channel registers must be 16-bit I/O-type accesses in the I/O space. Byte accesses result in erroneous operation.

Each CAN channel has 62, 16-bit registers. These registers allow for configuration, control, status, and operational data. Table 5-3the 16-bit register mapping for both CAN channels of these registers. The hex offsets shown in the table are offset from the base addresses in Table 5-2.

Register Summary

Table 5-3. CAN Channel Register Summary

Hex Offset

 

Register

00

 

TxMessage_0: ID, ID28-13

02

 

ID12-00

04

 

TxMessage_0: Data, D55-48, D63-56

06

 

D39-32, D47-40

08

 

D23-16, D31-24

0A

 

D07-00, D15-08

0C

 

TxMessage_0: RTR, IDE, DLC_3-0

0E

 

TxMessage_0: Control Flags, TXAbort, TRX

10

 

TxMessage_1: ID, ID28-13

12

 

ID12-00

14

 

TxMessage_1: Data, D55-48, D63-56

16

 

D39-32, D47-40

18

 

D23-16, D31-24

1A

 

D07-00, D15-08

1C

 

TxMessage_1: RTR, IDE, DLC_3-0

1E

 

TxMessage_1: Control Flags, TXAbort, TRX

20

 

TxMessage_2: ID, ID28-13

22

 

ID12-00

24

 

TxMessage_2: Data, D55-48, D63-56

26

 

D39-32, D47-40

28

 

D23-16, D31-24

2A

 

D07-00, D15-08

2C

 

TxMessage_2: RTR, IDE, DLC_3-0

2E

 

TxMessage_2: Control Flags, TXAbort, TRX

 

58

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Contents DSTni-EX User Guide Section FivePage Technical Support Copyright & TrademarkLantronix Master DistributorWarranty 2 SPI Controller Contents1 About This User Guide 3 I2C ControllerList of Tables 5 CAN ControllersTable 3-17. Clock Control Register List of Figures 1 About This User Guide Navigating Online Intended AudienceConventions Notes Notes are information requiring attentionOrganization SPI Background 2 SPI ControllerTheory of Operation DSTni SPI ControllerSPI Controller Register Summary Table 2-1. SPI Controller Register SummaryRESET SPI Controller Register DefinitionsSPIDATA Register Table 2-2. SPIDATA RegisterPhase Select CTL RegisterInterrupt Request Enable Wire-OTable 2-7. SPISTAT Register Definitions SPISTAT RegisterTable 2-6. SPISTAT Register Interrupt RequestSelectO Signal SPISSEL RegisterTable 2-10. BCNT Bit Settings Table 2-8. SPISSEL RegisterTable 2-11. DVDCNTRLO Register DVDCNTRLO RegisterDVDCNTRHI Table 2-12. DVDCNTRLO Register DefinitionsFeatures 3 I2C ControllerBlock Diagram I2C BackgroundFigure 3-1. DSTni I2C Controller Block Diagram I2C Controller Operating ModesMaster Transmit Mode I2C State Table 3-1. Master Transmit Status CodesCode Microprocessor ResponseServicing the Interrupt Table 3-2. Codes After Servicing Interrupts Master TransmitAll Bytes Transmit Completely Transmitting Each Data ByteTable 3-3. Status Codes After Each Data Byte Transmits Master Receive ModeTable 3-4. Master Receive Status Codes Table 3-5. Codes After Servicing Interrupt Master Receive Receiving Each Data Byte Table 3-6. Codes After Receiving Each Data ByteSlave Transmit Mode Slave Receive Mode Clock Synchronization Bus Clock ConsiderationsBus Clock Speed Bus ArbitrationResetting the I2C Controller Programmer’s ReferenceI2C Controller Register Summary Table 3-7. I 2C Controller Register SummaryGeneral Call Address Enable I2C Controller Register DefinitionsSlave Address Register Table 3-8. Slave Address RegisterData Register Table 3-10. Data RegisterTable 3-13. Control Register Definitions Control RegisterTable 3-12. Control Register Extended Slave AddressStatus Register Table 3-14. Status RegisterTable 3-15. Status Register Definitions Table 3-16. Status CodesStatus Code Clock Control Register Table 3-17. Clock Control RegisterTable 3-18. Clock Control Register Definitions Table 3-21. Software Reset Register Software Reset RegisterExtended Slave Address Register Table 3-22. Software Reset Register Definitions4 USB Controller USB Core USB BackgroundUSB Interrupt Serial Interface EngineMicroprocessor Interface USB Hardware/Software InterfaceDigital Phase Lock Loop Logic Buffer Descriptor TableFigure 4-1. Buffer Descriptor Table Rx vs. Tx as a Target Device or HostTable 4-2. 16-Bit USB Address Table 4-1. USB Data DirectionAddressing BDT Entries Table 4-3. 16-Bit USB Address DefinitionsMicroprocessor Determines… Table 4-4. BDT Data Used by USB Controller and MicroprocessorUSB Controller Determines… Table 4-5. USB Buffer Descriptor FormatDATA0/1 Transmit or Receive Table 4-6. USB Buffer Descriptor Format DefinitionsBD Owner USB OwnershipUSB Transaction Figure 4-2. USB Token TransactionUSB Register Summary Table 4-7. USB Register SummaryDedicated to host mode Table 4-8. Interrupt Status Register USB Register DefinitionsInterrupt Status Register Table 4-9. 16- Interrupt Status Register DefinitionsError Condition Enable/Disable USBRST InterruptSleep Timer USB ResetError Register Table 4-10. Error Interrupt Status RegisterTable 4-11. 16- Error Interrupt Status Register Definitions CRC16 Failure Error interrupt with two functionsData Field Received Not 8 Bits PID check field failedTable 4-12. Status Register Live USB Differential Receiver JSTATE SignalLive USB Single Ended Zero Signal Table 4-13. Status Register DefinitionsResume Signaling USB Reset SignalHost Mode Enable valid for host mode only BDT PDD ResetAddress Register Table 4-14. Address RegisterTable 4-15. 16- Address Register Definitions Table 4-17. Frame Number Register Definitions Frame Number RegistersTable 4-16. Frame Number Register Frame NumberToken Register Table 4-19. Token Register Definitions Endpoint for Token CommandTable 4-18. Token Register Table 4-20. Valid PID TokensTable 4-21. Endpoint Control Registers Endpoint Control RegistersEndpoint Enable Table 4-22. Endpoint Control Register DefinitionsHost Mode Operation Table 4-23. Endpoint Control Register DefinitionsSample Host Mode Operations Figure 3. Enable Host Mode and Configure a Target DeviceFigure 4. Full-Speed Bulk Data Transfers to a Target Device USB Pull-up/Pull-down Resistors Figure 4-5. Pull-up/Pull-down USBHOST Mode Enable USB Interface SignalsUSB Output Enable Clock CLK5 CAN Controllers Arbitration and Error Checking CANBUS BackgroundData Exchanges and Communication CANBUS Speed and Length Table 5-1. Bit Rates for Different Cable LengthsHex Offset CAN Register SummariesRegister Summary RegisterHex Offset Detailed CAN Register Map Table 5-4. Detailed CAN Register MapAcceptance Filter Enable Register Hex OffsetRegister Figure 5-1. TX Message Routing CAN Register DefinitionsTX Message Registers Sending a MessageTable 5-6. TxMessage0ID12 Tx Message RegistersTable 5-5. TxMessage0ID28 Table 5-7. TxMessage0DataMessage Identifier for Both Standard and Extended Messages Table 5-12. TxMessage0Ctrl FlagsTable 5-13. TxMessage0 Register Definitions Message DataRX Message Registers Figure 5-2. RX Message RoutingTable 5-15. Rx Message ID28 Register Definitions Rx Message RegistersTable 5-14. RxMessageID28 Table 5-16. RxMessageID12Table 5-22. Rx Message Data Table 5-20. Rx Message DataTable 5-21. Rx Message Data 39 Register Definitions Table 5-23. Rx Message Data 23 Register DefinitionsTable 5-28. Rx Message Msg Flags Table 5-26. RxMessage RTRTable 5-27. Rx Message RTR Register Definitions Table 5-29. Rx Message Msg Flags Register DefinitionsTable 5-31. Tx\Rx Error Count Register Definitions Error Count and Status RegistersTable 5-30. Tx/Rx Error Count Table 5-32. Error Statusrxlevel10 Table 5-34. Tx/Rx Message Level RegisterTable 5-35. Tx/Rx Message Level Register Definitions txlevel10CRC Error Interrupt FlagsNote The reset value of this register’s bits is indeterminate Format ErrorTable 5-39. Interrupt Enable Register Definitions Interrupt Enable RegistersTable 5-38. Interrupt Enable Registers Bus Off State − int2n group error interruptsTable 5-41. Interrupt Enable Register Definitions CAN Operating ModeTable 5-40. Interrupt Enable Registers Overload Condition − int3n group diagnostic interruptsFigure 5-3. CAN Operating Mode CAN Configuration RegistersConfiguration Bit Rate Table 5-42. Bit Rate Divisor RegisterOverwrite Last Message Table 5-44. Configuration RegisterTable 5-45. Configuration Register Definitions Cfgsjwtseg2 + Bit Timetseg1 + time quanta TQTable 5-47. Acceptance Filter Enable Register Definitions Acceptance Filter and Acceptance Code MaskTable 5-46. Acceptance Filter Enable Register Table 5-48. Acceptance Mask 0 RegisterTable 5-52. Acceptance Mask Register Data Table 5-50. Acceptance Mask Register IDTable 5-51. Acceptance Mask Register ID12 Definitions D5556Table 5-56. Acceptance Mask Register ID12 Table 5-54. Acceptance Code RegisterTable 5-55. Acceptance Code Register Definitions Table 5-57. Acceptance Mask Register ID12 DefinitionsTable 5-60. Arbitration Lost Capture Register CANbus AnalysisArbitration Lost Capture Register Table 5-61. Arbitration Lost Capture Register DefinitionsTable 5-63. Error Capture Register Definitions Error Capture RegisterTable 5-62. Error Capture Register ErrorcodeTable 5-64. Frame Reference Register Table 5-65. Error Capture Register DefinitionsFrame Reference Register Stuff Bit InsertedFigure 5-6. CAN Connector CAN Bus InterfaceInterface Connections Figure 5-5. CAN Bus InterfaceGNDCAN Figure 5-7. Power for CAN+5CAN +24VFigure 5-8. CAN Transceiver and Isolation Circuits 0.01uf
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