I2C Controller
The I2C controller base address is D000h and shares INT2 with the SPI controller. The I2C bus interface requires two
Operating Modes
The following sections describe the possible I2C operating modes:
Master Transmit Mode, page 13
Master Receive Mode, page 16
Slave Transmit Mode, page 19
Slave Receive Mode, page 20
Master Transmit Mode
In master transmit mode, the I2C controller transmits a number of bytes to a slave receiver. To enter the master transmit mode, set the STA bit to one. The following actions occur:
1.The DATA register loads either a
2.The M I2C tests the I2C bus and sends a START condition when the bus is free.
3.The IFLG bit is set and the status code in the Status register becomes 08h.
4.The IFLG bit clears to zero to prompt the transfer to continue.
5.After the
During this sequence, a number of status codes are possible in the Status register (see Table
Note: In
13