Lantronix DSTni-EX 21. Endpoint Control Registers, 22. Endpoint Control Register Definitions

Page 57
Endpoint Control Registers

Endpoint Control Registers

The Endpoint Control registers contain the endpoint control bits for the 16 endpoints available on USB for a decoded address. These four bits define all the control necessary for any one endpoint. Endpoint 0 (ENDPT0) is associated with control pipe 0, which is required by USB for all functions. Therefore, after receiving a USB_RST interrupt, the microprocessor sets ENDPT0 to contain 0Dh.

Table 4-21. Endpoint Control Registers

 

BIT

 

7

6

5

 

4

3

 

2

1

0

 

OFFSET

 

 

 

 

 

11h through 7h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FIELDS

 

WOHOST_ _HUB

RETRY_DIS

///

 

CTLEP__DIS

RXEP__EN

 

TXEP__EN

STALLEP_

HSHKEP_

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RESET

 

0

0

0

 

0

0

 

0

0

0

 

RW

 

R/W

R/W

R/W

 

R/W

R/W

 

R/W

R/W

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 4-22. Endpoint Control Register Definitions

 

 

 

 

 

 

 

 

Bits

 

Field Name

 

 

Description

 

7

 

HOST_WO_HUB

 

 

Host-Mode-Only Bit

 

 

 

 

 

 

A host-mode-only bit that is present only in the Control register for endpoint 0

 

 

 

 

 

 

(endpt0_rg).

 

 

 

 

 

 

1 = host can communicate to a directly connected low-speed device.

 

 

 

 

 

 

0 = host produces the PRE_PID, then switches to low-speed signaling to send a

 

 

 

 

 

 

token to a low-speed device. This is required to communicate with a low-speed

 

 

 

 

 

 

device through a hub.

 

6

 

RETRY_DIS

 

 

Host-Mode-Only Bit

 

 

 

 

 

 

A host-mode-only bit that is present only in the control register for endpoint 0

 

 

 

 

 

 

(endpt0_rg).

 

 

 

 

 

 

1 = prevent host retrying NAK’ed transactions. When a transaction is NAK'ed, the

 

 

 

 

 

 

NAK PID updates the BDT PID field and the token-done interrupt is set.

 

 

 

 

 

 

(Required setting when host tries to poll an interrupt endpoint.)

 

 

 

 

 

 

0 = NAK'ed transactions are retried in hardware.

 

5

///

 

 

Reserved

 

4

 

EP_CTL_ DIS

 

 

Endpoint Enable

 

3

 

EP_RX_EN

 

 

Defines whether an endpoint is enabled and the direction of the endpoint. Table

 

2

 

EP_TX_EN

 

 

4-23shows the enable/direction control values.

 

 

 

 

 

 

1

 

EP_STALL

 

 

Endpoint Stalled

 

 

 

 

 

 

This bit has priority over all control bits in the Endpoint Enable register; however,

 

 

 

 

 

 

it is only valid if EP_IN_EN=1 or EP_OUT_EN=1. Any access to this endpoint

 

 

 

 

 

 

causes the USB to return a STALL handshake. After an endpoint stalls, it requires

 

 

 

 

 

 

intervention from the host controller.

 

0

 

EP_HSHK

 

 

Endpoint Handshaking

 

 

 

 

 

 

1 = defines whether the endpoint performs handshaking during a transaction to

 

 

 

 

 

 

this endpoint

 

 

 

 

 

 

This bit is generally set, unless it is an isochronous endpoint.

49

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Contents Section Five DSTni-EX User GuidePage Lantronix Copyright & TrademarkTechnical Support Master DistributorWarranty 1 About This User Guide Contents2 SPI Controller 3 I2C Controller5 CAN Controllers List of TablesTable 3-17. Clock Control Register List of Figures 1 About This User Guide Conventions Intended AudienceNavigating Online Notes Notes are information requiring attentionOrganization Theory of Operation 2 SPI ControllerSPI Background DSTni SPI ControllerTable 2-1. SPI Controller Register Summary SPI Controller Register SummarySPIDATA Register SPI Controller Register DefinitionsRESET Table 2-2. SPIDATA RegisterInterrupt Request Enable CTL RegisterPhase Select Wire-OTable 2-6. SPISTAT Register SPISTAT RegisterTable 2-7. SPISTAT Register Definitions Interrupt RequestTable 2-10. BCNT Bit Settings SPISSEL RegisterSelectO Signal Table 2-8. SPISSEL RegisterDVDCNTRHI DVDCNTRLO RegisterTable 2-11. DVDCNTRLO Register Table 2-12. DVDCNTRLO Register Definitions3 I2C Controller FeaturesBlock Diagram I2C BackgroundFigure 3-1. DSTni I2C Controller Block Diagram I2C Controller Operating ModesMaster Transmit Mode Code Table 3-1. Master Transmit Status CodesI2C State Microprocessor ResponseTable 3-2. Codes After Servicing Interrupts Master Transmit Servicing the InterruptTable 3-3. Status Codes After Each Data Byte Transmits Transmitting Each Data ByteAll Bytes Transmit Completely Master Receive ModeTable 3-4. Master Receive Status Codes Table 3-5. Codes After Servicing Interrupt Master Receive Receiving Each Data Byte Table 3-6. Codes After Receiving Each Data ByteSlave Transmit Mode Slave Receive Mode Bus Clock Speed Bus Clock ConsiderationsClock Synchronization Bus ArbitrationI2C Controller Register Summary Programmer’s ReferenceResetting the I2C Controller Table 3-7. I 2C Controller Register SummarySlave Address Register I2C Controller Register DefinitionsGeneral Call Address Enable Table 3-8. Slave Address RegisterTable 3-10. Data Register Data RegisterTable 3-12. Control Register Control RegisterTable 3-13. Control Register Definitions Extended Slave AddressTable 3-14. Status Register Status RegisterTable 3-15. Status Register Definitions Table 3-16. Status CodesStatus Code Clock Control Register Table 3-17. Clock Control RegisterTable 3-18. Clock Control Register Definitions Extended Slave Address Register Software Reset RegisterTable 3-21. Software Reset Register Table 3-22. Software Reset Register Definitions4 USB Controller USB Interrupt USB BackgroundUSB Core Serial Interface EngineDigital Phase Lock Loop Logic USB Hardware/Software InterfaceMicroprocessor Interface Buffer Descriptor TableRx vs. Tx as a Target Device or Host Figure 4-1. Buffer Descriptor TableAddressing BDT Entries Table 4-1. USB Data DirectionTable 4-2. 16-Bit USB Address Table 4-3. 16-Bit USB Address DefinitionsUSB Controller Determines… Table 4-4. BDT Data Used by USB Controller and MicroprocessorMicroprocessor Determines… Table 4-5. USB Buffer Descriptor FormatBD Owner Table 4-6. USB Buffer Descriptor Format DefinitionsDATA0/1 Transmit or Receive USB OwnershipFigure 4-2. USB Token Transaction USB TransactionUSB Register Summary Table 4-7. USB Register SummaryDedicated to host mode Interrupt Status Register USB Register DefinitionsTable 4-8. Interrupt Status Register Table 4-9. 16- Interrupt Status Register DefinitionsSleep Timer Enable/Disable USBRST InterruptError Condition USB ResetError Register Table 4-10. Error Interrupt Status RegisterTable 4-11. 16- Error Interrupt Status Register Definitions Data Field Received Not 8 Bits Error interrupt with two functionsCRC16 Failure PID check field failedLive USB Single Ended Zero Signal Live USB Differential Receiver JSTATE SignalTable 4-12. Status Register Table 4-13. Status Register DefinitionsHost Mode Enable valid for host mode only USB Reset SignalResume Signaling BDT PDD ResetAddress Register Table 4-14. Address RegisterTable 4-15. 16- Address Register Definitions Table 4-16. Frame Number Register Frame Number RegistersTable 4-17. Frame Number Register Definitions Frame NumberToken Register Table 4-18. Token Register Endpoint for Token CommandTable 4-19. Token Register Definitions Table 4-20. Valid PID TokensEndpoint Enable Endpoint Control RegistersTable 4-21. Endpoint Control Registers Table 4-22. Endpoint Control Register DefinitionsTable 4-23. Endpoint Control Register Definitions Host Mode OperationFigure 3. Enable Host Mode and Configure a Target Device Sample Host Mode OperationsFigure 4. Full-Speed Bulk Data Transfers to a Target Device Figure 4-5. Pull-up/Pull-down USB USB Pull-up/Pull-down ResistorsUSB Output Enable USB Interface SignalsHOST Mode Enable Clock CLK5 CAN Controllers Arbitration and Error Checking CANBUS BackgroundData Exchanges and Communication Table 5-1. Bit Rates for Different Cable Lengths CANBUS Speed and LengthRegister Summary CAN Register SummariesHex Offset RegisterRegister Table 5-4. Detailed CAN Register Map Detailed CAN Register MapHex Offset Acceptance Filter Enable RegisterRegister TX Message Registers CAN Register DefinitionsFigure 5-1. TX Message Routing Sending a MessageTable 5-5. TxMessage0ID28 Tx Message RegistersTable 5-6. TxMessage0ID12 Table 5-7. TxMessage0DataTable 5-13. TxMessage0 Register Definitions Table 5-12. TxMessage0Ctrl FlagsMessage Identifier for Both Standard and Extended Messages Message DataFigure 5-2. RX Message Routing RX Message RegistersTable 5-14. RxMessageID28 Rx Message RegistersTable 5-15. Rx Message ID28 Register Definitions Table 5-16. RxMessageID12Table 5-21. Rx Message Data 39 Register Definitions Table 5-20. Rx Message DataTable 5-22. Rx Message Data Table 5-23. Rx Message Data 23 Register DefinitionsTable 5-27. Rx Message RTR Register Definitions Table 5-26. RxMessage RTRTable 5-28. Rx Message Msg Flags Table 5-29. Rx Message Msg Flags Register DefinitionsTable 5-30. Tx/Rx Error Count Error Count and Status RegistersTable 5-31. Tx\Rx Error Count Register Definitions Table 5-32. Error StatusTable 5-35. Tx/Rx Message Level Register Definitions Table 5-34. Tx/Rx Message Level Registerrxlevel10 txlevel10Note The reset value of this register’s bits is indeterminate Interrupt FlagsCRC Error Format ErrorTable 5-38. Interrupt Enable Registers Interrupt Enable RegistersTable 5-39. Interrupt Enable Register Definitions Bus Off State − int2n group error interruptsTable 5-40. Interrupt Enable Registers CAN Operating ModeTable 5-41. Interrupt Enable Register Definitions Overload Condition − int3n group diagnostic interruptsConfiguration Bit Rate CAN Configuration RegistersFigure 5-3. CAN Operating Mode Table 5-42. Bit Rate Divisor RegisterTable 5-45. Configuration Register Definitions Table 5-44. Configuration RegisterOverwrite Last Message Cfgsjwtseg1 + Bit Timetseg2 + time quanta TQTable 5-46. Acceptance Filter Enable Register Acceptance Filter and Acceptance Code MaskTable 5-47. Acceptance Filter Enable Register Definitions Table 5-48. Acceptance Mask 0 RegisterTable 5-51. Acceptance Mask Register ID12 Definitions Table 5-50. Acceptance Mask Register IDTable 5-52. Acceptance Mask Register Data D5556Table 5-55. Acceptance Code Register Definitions Table 5-54. Acceptance Code RegisterTable 5-56. Acceptance Mask Register ID12 Table 5-57. Acceptance Mask Register ID12 DefinitionsArbitration Lost Capture Register CANbus AnalysisTable 5-60. Arbitration Lost Capture Register Table 5-61. Arbitration Lost Capture Register DefinitionsTable 5-62. Error Capture Register Error Capture RegisterTable 5-63. Error Capture Register Definitions ErrorcodeFrame Reference Register Table 5-65. Error Capture Register DefinitionsTable 5-64. Frame Reference Register Stuff Bit InsertedInterface Connections CAN Bus InterfaceFigure 5-6. CAN Connector Figure 5-5. CAN Bus Interface+5CAN Figure 5-7. Power for CANGNDCAN +24V0.01uf Figure 5-8. CAN Transceiver and Isolation Circuits
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