Lantronix DSTni-EX manual 6. USB Buffer Descriptor Format Definitions, BD Owner, USB Ownership

Page 44

Table 4-6. USB Buffer Descriptor Format Definitions

Bits

Field Name

Description

7

OWN

BD Owner

 

 

Specifies which unit has exclusive access to the BD.

 

 

0 = microprocessor has exclusive and entire BD access; USB ignores all other

 

 

fields in the BD

 

 

1 = USB has exclusive BD access SIE writes a 0 to this bit when it completes a

 

 

token, except when KEEP=1. This byte must always be the last byte the

 

 

microprocessor updates when it initializes a BD. After the BD is assigned to the

 

 

USB, the microprocessor must not change it.

6

DATA0/1

DATA0/1 Transmit or Receive

 

 

Transmission or reception of a DATA0 or DATA1 field.

 

 

0 = transmission or reception of a DATA0 field.

 

 

1 = transmission or reception of a DATA1 field.

 

 

The USB does not change this value.

5

USB_OWN

USB Ownership

 

 

1 = once the OWN bit is set, the USB owns it forever.

 

 

0 = USB can release the BD when a token is processed.

 

 

Typically, this bit is set to 1 with ISO endpoints that feed a FIFO. The

 

 

microprocessor is not informed of the token processing. Instead, the process is

 

 

a simple data transfer to or from the FIFO.

 

 

When this bit is set to1:

 

 

• The NINC bit is usually set to prevent the address from incrementing.

 

 

• The USB does not change this bit; otherwise the USB writes bit 3 of the

 

 

current token PID back to the BD.

4

NINC

No Increment Bit

 

 

Disables DMA engine address incrementation, forcing the DMA engine to read

 

 

or write from the same address. This is useful for endpoints when data must be

 

 

read from or written to a single location such as a FIFO. Typically, this bit is set

 

 

with the USB_OWN bit for ISO endpoints that interface with a FIFO. If

 

 

USB_OWN=1, the USB does not change this bit; otherwise, the USB writes bit

 

 

2 of the current token PID to the BD.

3

DTS

Data Toggle Synchronization

 

 

0 = USB cannot perform Data Toggle Synchronization.

 

 

1 = USB can perform Data Toggle Synchronization.

 

 

If USB_OWN=1, the USB does not change this bit; otherwise, the USB writes

 

 

bit 1 of the current token PID to the BD.

1:0

BCH[9:8]

Byte Count High Bits

 

 

Represent the high-order bits of the 10-bit byte count. The USB SIE changes

 

 

this field after completing an RX transfer with the byte count of the data

 

 

received.

7:0

BCL

Byte Count Low Bits

 

 

Represent the low-order byte of the 10-bit byte count. BCH and BCL together

 

 

form the 10-bit byte count. This represents the number of bytes to transmit for

 

 

a TX transfer or receive during an RX transfer. Valid byte counts are 0 to 1023.

 

 

The USB SIE changes this field after completing an RX transfer with the actual

 

 

byte count of the data received.

7:0

ADDR[31:0]

Address Bits

(Bytes 4

 

Represent the 32-bit buffer address in system memory. DSTni only uses the

through 2 and

 

lower 24 bits to form the address where the buffer resides in system memory.

Low Byte)

 

This is the address that the USB DMA engine uses when it reads or writes

 

 

data. The USB does not change these bits.

36

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Contents DSTni-EX User Guide Section FivePage Copyright & Trademark LantronixTechnical Support Master DistributorWarranty Contents 1 About This User Guide2 SPI Controller 3 I2C ControllerList of Tables 5 CAN ControllersTable 3-17. Clock Control Register List of Figures 1 About This User Guide Intended Audience ConventionsNavigating Online Notes Notes are information requiring attentionOrganization 2 SPI Controller Theory of OperationSPI Background DSTni SPI ControllerSPI Controller Register Summary Table 2-1. SPI Controller Register SummarySPI Controller Register Definitions SPIDATA RegisterRESET Table 2-2. SPIDATA RegisterCTL Register Interrupt Request EnablePhase Select Wire-OSPISTAT Register Table 2-6. SPISTAT RegisterTable 2-7. SPISTAT Register Definitions Interrupt RequestSPISSEL Register Table 2-10. BCNT Bit SettingsSelectO Signal Table 2-8. SPISSEL RegisterDVDCNTRLO Register DVDCNTRHITable 2-11. DVDCNTRLO Register Table 2-12. DVDCNTRLO Register DefinitionsFeatures 3 I2C ControllerFigure 3-1. DSTni I2C Controller Block Diagram Block DiagramI2C Background Master Transmit Mode I2C ControllerOperating Modes Table 3-1. Master Transmit Status Codes CodeI2C State Microprocessor ResponseServicing the Interrupt Table 3-2. Codes After Servicing Interrupts Master TransmitTransmitting Each Data Byte Table 3-3. Status Codes After Each Data Byte TransmitsAll Bytes Transmit Completely Master Receive ModeTable 3-4. Master Receive Status Codes Table 3-5. Codes After Servicing Interrupt Master Receive Slave Transmit Mode Receiving Each Data ByteTable 3-6. Codes After Receiving Each Data Byte Slave Receive Mode Bus Clock Considerations Bus Clock SpeedClock Synchronization Bus ArbitrationProgrammer’s Reference I2C Controller Register SummaryResetting the I2C Controller Table 3-7. I 2C Controller Register SummaryI2C Controller Register Definitions Slave Address RegisterGeneral Call Address Enable Table 3-8. Slave Address RegisterData Register Table 3-10. Data RegisterControl Register Table 3-12. Control RegisterTable 3-13. Control Register Definitions Extended Slave AddressStatus Register Table 3-14. Status RegisterStatus Code Table 3-15. Status Register DefinitionsTable 3-16. Status Codes Table 3-18. Clock Control Register Definitions Clock Control RegisterTable 3-17. Clock Control Register Software Reset Register Extended Slave Address RegisterTable 3-21. Software Reset Register Table 3-22. Software Reset Register Definitions4 USB Controller USB Background USB InterruptUSB Core Serial Interface EngineUSB Hardware/Software Interface Digital Phase Lock Loop LogicMicroprocessor Interface Buffer Descriptor TableFigure 4-1. Buffer Descriptor Table Rx vs. Tx as a Target Device or HostTable 4-1. USB Data Direction Addressing BDT EntriesTable 4-2. 16-Bit USB Address Table 4-3. 16-Bit USB Address DefinitionsTable 4-4. BDT Data Used by USB Controller and Microprocessor USB Controller Determines…Microprocessor Determines… Table 4-5. USB Buffer Descriptor FormatTable 4-6. USB Buffer Descriptor Format Definitions BD OwnerDATA0/1 Transmit or Receive USB OwnershipUSB Transaction Figure 4-2. USB Token TransactionDedicated to host mode USB Register SummaryTable 4-7. USB Register Summary USB Register Definitions Interrupt Status RegisterTable 4-8. Interrupt Status Register Table 4-9. 16- Interrupt Status Register DefinitionsEnable/Disable USBRST Interrupt Sleep TimerError Condition USB ResetTable 4-11. 16- Error Interrupt Status Register Definitions Error RegisterTable 4-10. Error Interrupt Status Register Error interrupt with two functions Data Field Received Not 8 BitsCRC16 Failure PID check field failedLive USB Differential Receiver JSTATE Signal Live USB Single Ended Zero SignalTable 4-12. Status Register Table 4-13. Status Register DefinitionsUSB Reset Signal Host Mode Enable valid for host mode onlyResume Signaling BDT PDD ResetTable 4-15. 16- Address Register Definitions Address RegisterTable 4-14. Address Register Frame Number Registers Table 4-16. Frame Number RegisterTable 4-17. Frame Number Register Definitions Frame NumberToken Register Endpoint for Token Command Table 4-18. Token RegisterTable 4-19. Token Register Definitions Table 4-20. Valid PID TokensEndpoint Control Registers Endpoint EnableTable 4-21. Endpoint Control Registers Table 4-22. Endpoint Control Register DefinitionsHost Mode Operation Table 4-23. Endpoint Control Register DefinitionsSample Host Mode Operations Figure 3. Enable Host Mode and Configure a Target DeviceFigure 4. Full-Speed Bulk Data Transfers to a Target Device USB Pull-up/Pull-down Resistors Figure 4-5. Pull-up/Pull-down USBUSB Interface Signals USB Output EnableHOST Mode Enable Clock CLK5 CAN Controllers Data Exchanges and Communication Arbitration and Error CheckingCANBUS Background CANBUS Speed and Length Table 5-1. Bit Rates for Different Cable LengthsCAN Register Summaries Register SummaryHex Offset RegisterHex Offset Detailed CAN Register Map Table 5-4. Detailed CAN Register MapAcceptance Filter Enable Register Hex OffsetRegister CAN Register Definitions TX Message RegistersFigure 5-1. TX Message Routing Sending a MessageTx Message Registers Table 5-5. TxMessage0ID28Table 5-6. TxMessage0ID12 Table 5-7. TxMessage0DataTable 5-12. TxMessage0Ctrl Flags Table 5-13. TxMessage0 Register DefinitionsMessage Identifier for Both Standard and Extended Messages Message DataRX Message Registers Figure 5-2. RX Message RoutingRx Message Registers Table 5-14. RxMessageID28Table 5-15. Rx Message ID28 Register Definitions Table 5-16. RxMessageID12Table 5-20. Rx Message Data Table 5-21. Rx Message Data 39 Register DefinitionsTable 5-22. Rx Message Data Table 5-23. Rx Message Data 23 Register DefinitionsTable 5-26. RxMessage RTR Table 5-27. Rx Message RTR Register DefinitionsTable 5-28. Rx Message Msg Flags Table 5-29. Rx Message Msg Flags Register DefinitionsError Count and Status Registers Table 5-30. Tx/Rx Error CountTable 5-31. Tx\Rx Error Count Register Definitions Table 5-32. Error StatusTable 5-34. Tx/Rx Message Level Register Table 5-35. Tx/Rx Message Level Register Definitionsrxlevel10 txlevel10Interrupt Flags Note The reset value of this register’s bits is indeterminateCRC Error Format ErrorInterrupt Enable Registers Table 5-38. Interrupt Enable RegistersTable 5-39. Interrupt Enable Register Definitions Bus Off State − int2n group error interruptsCAN Operating Mode Table 5-40. Interrupt Enable RegistersTable 5-41. Interrupt Enable Register Definitions Overload Condition − int3n group diagnostic interruptsCAN Configuration Registers Configuration Bit RateFigure 5-3. CAN Operating Mode Table 5-42. Bit Rate Divisor RegisterTable 5-44. Configuration Register Table 5-45. Configuration Register DefinitionsOverwrite Last Message CfgsjwBit Time tseg1 +tseg2 + time quanta TQAcceptance Filter and Acceptance Code Mask Table 5-46. Acceptance Filter Enable RegisterTable 5-47. Acceptance Filter Enable Register Definitions Table 5-48. Acceptance Mask 0 RegisterTable 5-50. Acceptance Mask Register ID Table 5-51. Acceptance Mask Register ID12 DefinitionsTable 5-52. Acceptance Mask Register Data D5556Table 5-54. Acceptance Code Register Table 5-55. Acceptance Code Register DefinitionsTable 5-56. Acceptance Mask Register ID12 Table 5-57. Acceptance Mask Register ID12 DefinitionsCANbus Analysis Arbitration Lost Capture RegisterTable 5-60. Arbitration Lost Capture Register Table 5-61. Arbitration Lost Capture Register DefinitionsError Capture Register Table 5-62. Error Capture RegisterTable 5-63. Error Capture Register Definitions ErrorcodeTable 5-65. Error Capture Register Definitions Frame Reference RegisterTable 5-64. Frame Reference Register Stuff Bit InsertedCAN Bus Interface Interface ConnectionsFigure 5-6. CAN Connector Figure 5-5. CAN Bus InterfaceFigure 5-7. Power for CAN +5CANGNDCAN +24VFigure 5-8. CAN Transceiver and Isolation Circuits 0.01uf
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