Bus Clock Considerations
Bus Clock Speed
The I2C bus can be defined for bus clock speeds up to 100 Kb/s and up to 400 Kb/s in fast mode.
To detect START and STOP conditions on the bus, the M I2C must sample the I2C bus at least 10 times faster than the fastest master bus clock on the bus. The sampling frequency must be at least 1 MHz (4 MHz in
The CLK input clock frequency and the value in CCR bits 2 - 0 determine the I2C sampling frequency. When the I2C controller is in the master mode, it determines the frequency of the CLK input and the values in bits [2:0] and [6:3] of the Clock Control register (see Clock Control Register on page 28).
Clock Synchronization
If another device on the I2C bus drives the clock line when the I2C controller is in master mode, the I2C controller synchronizes its clock to the I2C bus clock.
The device that generates the shortest high clock period determines the high period of the clock.
The device that generates the longest LOW clock period determines the LOW period of the clock.
When the I2C controller is in master mode and is communicating with a slow slave, the slave can stretch each bit period by holding the SCL line LOW until it is ready for the next bit. When the I2C controller is in slave mode, it holds the SCL line LOW after each byte transfers until the IFLG clears in the Control register.
Bus Arbitration
In master mode, the I2C controller checks that each logical 1 transmitted appears on the I2C bus as a logical 1. If another device on the bus overrules and pulls the SDA line LOW, arbitration is lost.
If arbitration is lost:
While a data byte or
During the transmission of an address, the I2C controller switches to slave mode so that it can recognize its own slave address or the general call address.
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