Cypress CY7C64215 Register Reference, Register Mapping Tables, Register Conventions Description

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CY7C64215

Register Reference

The register conventions specific to this section are listed in the following table.

Table 4. Register Conventions

Convention

Description

R

Read register or bit(s)

 

 

W

Write register or bit(s)

 

 

L

Logical register or bit(s)

 

 

C

Clearable register or bit(s)

 

 

#

Access is bit specific

 

 

Register Mapping Tables

The enCoRe III device has a total register address space of 512 bytes. The register space is referred to as IO space and is divided into two banks. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user is in Bank 1.

Note In the following register mapping tables, blank fields are Reserved and should not be accessed.

Document 38-08036 Rev. *C

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Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesBlock Diagram San Jose, CA Document 38-08036 Rev. *C Revised December 08EnCoRe III Core ApplicationsEnCoRe III Functional Overview Digital SystemGetting Started EnCoRe III Device CharacteristicsEnCoRe III Device Characteristics Additional System ResourcesPSoC Designer Software Subsystems Development ToolsDevelopment Kits Device EditorDesigning with User Modules Hardware ToolsDebugger DeviceEditorApplicationEditor Generate ApplicationUnits of Measure Document ConventionsAcronyms Used Numeric NamingPin Part Pinout Pin Part Pinout MLF CY7C64215 56-Pin enCoRe III DeviceP07 Analog column mux input Pin Part Pinout SsopCY7C64215 28-Pin enCoRe III Device P05 Analog column mux input and column OutputRegister Mapping Tables Register ReferenceRegister Conventions Description Name Addr 0,Hex Access Register Map Bank 0 Table User SpaceRegister Map Bank 1 Table Configuration Space Name Addr Access HexElectrical Specifications Units of Measure Symbol Unit of MeasureAbsolute Maximum Ratings Operating TemperatureAbsolute Maximum Ratings Parameter Description Min Typ Unit DC Chip-Level Specifications DC Electrical CharacteristicsDC General Purpose IO Specifications DC Full-Speed USB Specifications DC Analog Output Buffer SpecificationsSupply Voltage Rejection Ratio DC Analog Reference SpecificationsP24 RefHi = P24 + P26 P24 = Vdd/2, P26 = P24 + P26 + DC Analog enCoRe III Block SpecificationsResistor Unit Value Continuous Time 12.2 P24 P26 P24 P26 +DC POR and LVD Specifications DC Programming Specifications AC Electrical Characteristics AC Chip-Level SpecificationsAC General Purpose IO Specifications AC Full-Speed USB SpecificationsAC Digital Block Specifications AC External Clock SpecificationsLarge Signal Bandwidth, 1Vpp, 3-dB BW, 100 pF Load AC Analog Output Buffer SpecificationsMHz Power = Low Power = High KHz Power = Low Power = HighAC Programming Specifications AC I2C SpecificationsSDA Package Diagrams Packaging InformationThermal Impedance Solder Reflow Peak TemperatureThermal Impedance for the Package Typical θ JA Parameter Description Min Typical Max Unit Package HandlingOrdering Information Ordering Code Flash Size Sram BytesSales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions