Cypress CY7C64215 manual AC Programming Specifications, AC I2C Specifications

Page 25

CY7C64215

AC Programming Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and 0°C < TA < 70°C, or 3.0V to 3.6V and 0°C < TA < 70°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only.

Table 25. AC Programming Specifications

Parameter

Description

Min

Typ

Max

Unit

Notes

TRSCLK

Rise Time of SCLK

1

–

20

ns

 

TFSCLK

Fall Time of SCLK

1

–

20

ns

 

TSSCLK

Data Set up Time to Falling Edge of SCLK

40

–

–

ns

 

THSCLK

Data Hold Time from Falling Edge of SCLK

40

–

–

ns

 

FSCLK

Frequency of SCLK

0

–

8

MHz

 

TERASEB

Flash Erase Time (Block)

–

10

–

ms

 

TWRITE

Flash Block Write Time

–

30

–

ms

 

TDSCLK

Data Out Delay from Falling Edge of SCLK

–

–

45

ns

Vdd > 3.6

TDSCLK3

Data Out Delay from Falling Edge of SCLK

–

–

50

ns

3.0 < Vdd < 3.6

AC I2C Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and 0°C < TA < 70°C, or 3.0V to 3.6V and 0°C < TA < 70°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only.

Table 26. AC Characteristics of the I2C SDA and SCL Pins for Vdd

Parameter

Description

Standard Mode

Fast Mode

Min

Max

Min

Max

 

 

 

 

Unit

Notes

FSCLI2C

SCL Clock Frequency

0

100

0

400

kHz

 

THDSTAI2C

Hold Time (repeated) START Condition. After

4.0

–

0.6

–

μs

 

 

this period, the first clock pulse is generated.

 

 

 

 

 

 

TLOWI2C

LOW Period of the SCL Clock

4.7

–

1.3

–

μs

 

THIGHI2C

HIGH Period of the SCL Clock

4.0

–

0.6

–

μs

 

TSUSTAI2C

Setup Time for a Repeated START Condition

4.7

–

0.6

–

μs

 

THDDATI2C

Data Hold Time

0

–

0

–

μs

 

TSUDATI2C

Data Setup Time

250

–

100[12]

–

ns

 

TSUSTOI2C

Setup Time for STOP Condition

4.0

–

0.6

–

μs

 

TBUFI2C

Bus Free Time Between a STOP and START

4.7

–

1.3

–

μs

 

 

Condition

 

 

 

 

 

 

TSPI2C

Pulse Width of spikes are suppressed by the

–

–

0

50

ns

 

 

input filter.

 

 

 

 

 

 

Note

12.A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT Š 250 ns must then be met. This automatically be the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.

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Contents Block Diagram FeaturesCypress Semiconductor Corporation 198 Champion Court San Jose, CA Document 38-08036 Rev. *C Revised December 08EnCoRe III Functional Overview ApplicationsEnCoRe III Core Digital SystemEnCoRe III Device Characteristics EnCoRe III Device CharacteristicsGetting Started Additional System ResourcesDevelopment Kits Development ToolsPSoC Designer Software Subsystems Device EditorHardware Tools Designing with User ModulesApplicationEditor DeviceEditorDebugger Generate ApplicationAcronyms Used Document ConventionsUnits of Measure Numeric NamingPin Part Pinout MLF CY7C64215 56-Pin enCoRe III Device Pin Part PinoutCY7C64215 28-Pin enCoRe III Device Pin Part Pinout SsopP07 Analog column mux input P05 Analog column mux input and column OutputRegister Mapping Tables Register ReferenceRegister Conventions Description Register Map Bank 0 Table User Space Name Addr 0,Hex AccessName Addr Access Hex Register Map Bank 1 Table Configuration SpaceUnits of Measure Symbol Unit of Measure Electrical SpecificationsAbsolute Maximum Ratings Operating TemperatureAbsolute Maximum Ratings Parameter Description Min Typ Unit DC Chip-Level Specifications DC Electrical CharacteristicsDC General Purpose IO Specifications DC Analog Output Buffer Specifications DC Full-Speed USB SpecificationsSupply Voltage Rejection Ratio DC Analog Reference SpecificationsP24 Resistor Unit Value Continuous Time 12.2 DC Analog enCoRe III Block SpecificationsRefHi = P24 + P26 P24 = Vdd/2, P26 = P24 + P26 + P24 P26 P24 P26 +DC POR and LVD Specifications DC Programming Specifications AC Chip-Level Specifications AC Electrical CharacteristicsAC Full-Speed USB Specifications AC General Purpose IO SpecificationsAC External Clock Specifications AC Digital Block SpecificationsMHz Power = Low Power = High AC Analog Output Buffer SpecificationsLarge Signal Bandwidth, 1Vpp, 3-dB BW, 100 pF Load KHz Power = Low Power = HighAC I2C Specifications AC Programming SpecificationsSDA Packaging Information Package DiagramsThermal Impedance Solder Reflow Peak TemperatureThermal Impedance for the Package Typical θ JA Ordering Information Package HandlingParameter Description Min Typical Max Unit Ordering Code Flash Size Sram BytesWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal Information
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