Cypress CY7C64215 manual Features, Block Diagram

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CY7C64215

enCoRe™ III Full Speed USB Controller

Features

Powerful Harvard Architecture Processor

M8C Processor Speeds to 24 MHz

Two 8x8 Multiply, 32-bit Accumulate

3.0V to 5.25V Operating Voltage

USB 2.0 USB-IF certified. TID# 40000110

Operating Temperature Range: 0°C to +70°C

Advanced Peripherals (enCoRe™ III Blocks)

6 Analog enCoRe III Blocks provide:

Up to 14-bit Incremental and Delta-Sigma ADCs

Programmable Threshold Comparator

4 Digital enCoRe III Blocks provide:

8-bit and 16-bit PWMs, timers and counters

I2C Master

SPI Master or Slave

Full Duplex UART

CYFISNP and CYFISPI modules to talk to Cypress CYFI radio

Complex Peripherals by Combining Blocks

Full-Speed USB (12 Mbps)

Four Unidirectional Endpoints

One Bidirectional Control Endpoint

Dedicated 256 Byte Buffer

No External Crystal Required

Operational at 3.0V – 3.6V or 4.35V – 5.25V

Flexible On-Chip Memory

16K Flash Program Storage 50,000 Erase/Write Cycles

1K SRAM Data Storage

In-System Serial Programming (ISSP)

Partial Flash Updates

Flexible Protection Modes

EEPROM Emulation in Flash

Programmable Pin Configurations

25-mA Sink on all GPIO

Pull up, Pull down, High- Z, Strong, or Open Drain Drive Modes on all GPIO

Configurable Interrupt on all GPIO

Precision, Programmable Clocking

Internal ±4% 24 and 48 MHz Oscillator

Internal Oscillator for Watchdog and Sleep

0.25% Accuracy for USB with no External Components

Additional System Resources

I2CSlave, Master, and Multi-Master to 400 kHz

Watchdog and Sleep Timers

User-Configurable Low Voltage Detection

Integrated Supervisory Circuit

On-Chip Precision Voltage Reference

Complete Development Tools

Free Development Software (PSoC® Designer)

Full-Featured, In-Circuit Emulator and Programmer

Full Speed Emulation

Complex Breakpoint Structure

128K Bytes Trace Memory

Block Diagram

enCoRe III Core

Cypress Semiconductor Corporation • 198 Champion Court

San Jose, CA 95134-1709

408-943-2600

Document 38-08036 Rev. *C

 

Revised December 08, 2008

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Contents Block Diagram FeaturesCypress Semiconductor Corporation 198 Champion Court San Jose, CA Document 38-08036 Rev. *C Revised December 08EnCoRe III Functional Overview ApplicationsEnCoRe III Core Digital SystemEnCoRe III Device Characteristics EnCoRe III Device CharacteristicsGetting Started Additional System ResourcesDevelopment Kits Development ToolsPSoC Designer Software Subsystems Device EditorHardware Tools Designing with User ModulesApplicationEditor DeviceEditorDebugger Generate ApplicationAcronyms Used Document ConventionsUnits of Measure Numeric NamingPin Part Pinout MLF CY7C64215 56-Pin enCoRe III Device Pin Part PinoutCY7C64215 28-Pin enCoRe III Device Pin Part Pinout SsopP07 Analog column mux input P05 Analog column mux input and column OutputRegister Mapping Tables Register ReferenceRegister Conventions Description Register Map Bank 0 Table User Space Name Addr 0,Hex AccessName Addr Access Hex Register Map Bank 1 Table Configuration SpaceUnits of Measure Symbol Unit of Measure Electrical SpecificationsAbsolute Maximum Ratings Operating TemperatureAbsolute Maximum Ratings Parameter Description Min Typ Unit DC Chip-Level Specifications DC Electrical CharacteristicsDC General Purpose IO Specifications DC Analog Output Buffer Specifications DC Full-Speed USB SpecificationsSupply Voltage Rejection Ratio DC Analog Reference SpecificationsP24 Resistor Unit Value Continuous Time 12.2 DC Analog enCoRe III Block SpecificationsRefHi = P24 + P26 P24 = Vdd/2, P26 = P24 + P26 + P24 P26 P24 P26 +DC POR and LVD Specifications DC Programming Specifications AC Chip-Level Specifications AC Electrical CharacteristicsAC Full-Speed USB Specifications AC General Purpose IO SpecificationsAC External Clock Specifications AC Digital Block SpecificationsMHz Power = Low Power = High AC Analog Output Buffer SpecificationsLarge Signal Bandwidth, 1Vpp, 3-dB BW, 100 pF Load KHz Power = Low Power = HighAC I2C Specifications AC Programming SpecificationsSDA Packaging Information Package DiagramsThermal Impedance Solder Reflow Peak TemperatureThermal Impedance for the Package Typical θ JA Ordering Information Package HandlingParameter Description Min Typical Max Unit Ordering Code Flash Size Sram BytesWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal Information