Cypress CY7C64215 manual Register Map Bank 1 Table Configuration Space, Name Addr Access Hex

CY7C64215

Register Map Bank 1 Table: Configuration Space

Name	Addr	Access	Name	Addr	Access	Name	Addr	Access	Name	Addr	Access
	(1,Hex)			(1,Hex)			(1,Hex)			(1,Hex)
PRT0DM0	00	RW	PMA0_WA	40	RW	ASC10CR0	80	RW	USBIO_CR2	C0	RW
PRT0DM1	01	RW	PMA1_WA	41	RW	ASC10CR1	81	RW	USB_CR1	C1	#
PRT0IC0	02	RW	PMA2_WA	42	RW	ASC10CR2	82	RW
PRT0IC1	03	RW	PMA3_WA	43	RW	ASC10CR3	83	RW
PRT1DM0	04	RW	PMA4_WA	44	RW	ASD11CR0	84	RW	EP1_CR0	C4	#
PRT1DM1	05	RW	PMA5_WA	45	RW	ASD11CR1	85	RW	EP2_CR0	C5	#
PRT1IC0	06	RW	PMA6_WA	46	RW	ASD11CR2	86	RW	EP3_CR0	C6	#
PRT1IC1	07	RW	PMA7_WA	47	RW	ASD11CR3	87	RW	EP4_CR0	C7	#
PRT2DM0	08	RW		48			88			C8
PRT2DM1	09	RW		49			89			C9
PRT2IC0	0A	RW		4A			8A			CA
PRT2IC1	0B	RW		4B			8B			CB
PRT3DM0	0C	RW		4C			8C			CC
PRT3DM1	0D	RW		4D			8D			CD
PRT3IC0	0E	RW		4E			8E			CE
PRT3IC1	0F	RW		4F			8F			CF
PRT4DM0	10	RW	PMA0_RA	50	RW		90		GDI_O_IN	D0	RW
PRT4DM1	11	RW	PMA1_RA	51	RW	ASD20CR1	91	RW	GDI_E_IN	D1	RW
PRT4IC0	12	RW	PMA2_RA	52	RW	ASD20CR2	92	RW	GDI_O_OU	D2	RW
PRT4IC1	13	RW	PMA3_RA	53	RW	ASD20CR3	93	RW	GDI_E_OU	D3	RW
PRT5DM0	14	RW	PMA4_RA	54	RW	ASC21CR0	94	RW		D4
PRT5DM1	15	RW	PMA5_RA	55	RW	ASC21CR1	95	RW		D5
PRT5IC0	16	RW	PMA6_RA	56	RW	ASC21CR2	96	RW		D6
PRT5IC1	17	RW	PMA7_RA	57	RW	ASC21CR3	97	RW		D7
	18			58			98		MUX_CR0	D8	RW
	19			59			99		MUX_CR1	D9	RW
	1A			5A			9A		MUX_CR2	DA	RW
	1B			5B			9B		MUX_CR3	DB	RW
PRT7DM0	1C	RW		5C			9C			DC
PRT7DM1	1D	RW		5D			9D		OSC_GO_EN	DD	RW
PRT7IC0	1E	RW		5E			9E		OSC_CR4	DE	RW
PRT7IC1	1F	RW		5F			9F		OSC_CR3	DF	RW
DBB00FN	20	RW	CLK_CR0	60	RW		A0		OSC_CR0	E0	RW
DBB00IN	21	RW	CLK_CR1	61	RW		A1		OSC_CR1	E1	RW
DBB00OU	22	RW	ABF_CR0	62	RW		A2		OSC_CR2	E2	RW
	23		AMD_CR0	63	RW		A3		VLT_CR	E3	RW
DBB01FN	24	RW	CMP_GO_EN	64	RW		A4		VLT_CMP	E4	R
DBB01IN	25	RW		65	RW		A5			E5
DBB01OU	26	RW	AMD_CR1	66	RW		A6			E6
	27		ALT_CR0	67	RW		A7			E7
DCB02FN	28	RW		68			A8		IMO_TR	E8	W
DCB02IN	29	RW		69			A9		ILO_TR	E9	W
DCB02OU	2A	RW		6A			AA		BDG_TR	EA	RW
	2B			6B			AB		ECO_TR	EB	W
DCB03FN	2C	RW	TMP_DR0	6C	RW		AC		MUX_CR4	EC	RW
DCB03IN	2D	RW	TMP_DR1	6D	RW		AD		MUX_CR5	ED	RW
DCB03OU	2E	RW	TMP_DR2	6E	RW		AE			EE
	2F		TMP_DR3	6F	RW		AF			EF
	30		ACB00CR3	70	RW	RDI0RI	B0	RW		F0
	31		ACB00CR0	71	RW	RDI0SYN	B1	RW		F1
	32		ACB00CR1	72	RW	RDI0IS	B2	RW		F2
	33		ACB00CR2	73	RW	RDI0LT0	B3	RW		F3
	34		ACB01CR3	74	RW	RDI0LT1	B4	RW		F4
	35		ACB01CR0	75	RW	RDI0RO0	B5	RW		F5
	36		ACB01CR1	76	RW	RDI0RO1	B6	RW		F6
	37		ACB01CR2	77	RW		B7		CPU_F	F7	RL
	38			78			B8			F8
	39			79			B9			F9
	3A			7A			BA			FA
	3B			7B			BB			FB
	3C			7C			BC			FC
	3D			7D			BD		DAC_CR	FD	RW
	3E			7E			BE		CPU_SCR1	FE	#
	3F			7F			BF		CPU_SCR0	FF	#
Blank fields are	Reserved	and should not be accessed.				# Access is bit specific.

Document 38-08036 Rev. *C Page 12 of 30

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