Cypress CYV15G0404RB manual Features, Functional Description, Cypress Semiconductor Corporation

CYV15G0404RB

Independent Clock Quad HOTLink II™ Deserializing Reclocker

Features

•Second-generation HOTLink® technology

•Compliant to SMPTE 292M and SMPTE 259M video standards

•Quad channel video reclocking deserializer

—195 to 1500 Mbps serial data signaling rate

—Simultaneous operation at different signaling rates

•Supports reception of either 1.485 or 1.485/1.001 Gbps data rate with the same training clock

•Supports half-rate and full-rate clocking

•Internal phase-locked loops (PLLs) with no external PLL components

•Selectable differential PECL-compatible serial inputs

—Internal DC restoration

•Synchronous LVTTL parallel interface

•JTAG boundary scan

•Built-In Self-Test (BIST) for at-speed link testing

•Link Quality Indicator

—Analog signal detect

—Digital signal detect

•Low-power: 3W @ 3.3V typical

•Single 3.3V supply

•Thermally enhanced BGA

•Pb-Free package option available

•0.25∝ BiCMOS technology

Functional Description

The CYV15G0404RB Independent Clock Quad HOTLink II™ Deserializing Reclocker is a point-to-point or point-to-multi- point communications building block enabling data transfer over a variety of high speed serial links including SMPTE 292

and SMPTE 259 video applications. It supports signaling rates in the range of 195 to 1500 Mbps for each serial link. The four channels are independent and can simultaneously operate at different rates. Each receive channel accepts serial data and converts it to 10-bit parallel characters and presents these characters to an Output Register. The received serial data can also be reclocked and retransmitted through the reclocker serial outputs. Figure 1, "HOTLink II™ System Connections," on page 2 illustrates typical connections between independent video coprocessors and corresponding CYV15G0404RB Reclocking Deserializer and CYV15G0403TB Serializer chips.

The CYV15G0404RB is SMPTE-259M and SMPTE-292M compliant according to SMPTE EG34-1999 Pathological Test Requirements.

As a second generation HOTLink device, the CYV15G0404RB extends the HOTLink family with enhanced levels of integration and faster data rates, while maintaining serial-link compatibility (data and BIST) with other HOTLink devices.

Each channel of the CYV15G0404RB Quad HOTLink II device accepts a serial bit-stream from one of two selectable PECL-compatible differential line receivers, and using a completely integrated Clock and Data Recovery PLL, recovers the timing information necessary for data reconstruction. The device reclocks and retransmits recovered bit-stream through the reclocker serial outputs. It also deserializes the recovered serial data and presents it to the destination host system.

Each channel contains an independent BIST pattern checker. This BIST hardware enables at speed testing of the high-speed serial data paths in each receive section of this device, each transmit section of a connected HOTLink II device, and across the interconnecting links.

The CYV15G0404RB is ideal for SMPTE applications where different data rates and serial interface standards are necessary for each channel. Some applications include multi-format routers, switchers, format converters, SDI monitors, and camera control units.

Cypress Semiconductor Corporation	• 198 Champion Court • San Jose, CA 95134-1709	•	408-943-2600
Document #: 38-02102 Rev. *C	Revised February 16, 2007

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