Cypress CYV15G0404RB manual Pin Configuration Top View1

Page 6

CYV15G0404RB

Pin Configuration (Top View)[1]

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

A

IN

ROUT

IN

ROUT

VCC

IN

ROUT

GND

IN

ROUT

IN

ROUT

GND

IN

ROUT

VCC

IN

ROUT

IN

ROUT

C1–

C1–

C2–

C2–

D1–

D1–

D2–

D2–

A1–

A1–

A2–

A2–

B1–

B1–

B2–

B2–

B

IN

ROUT

IN

ROUT

VCC

IN

ROUT

GND

IN

ROUT

IN

ROUT

GND

IN

ROUT

VCC

IN

ROUT

IN

ROUT

C1+

C1+

C2+

C2+

D1+

D1+

D2+

D2+

A1+

A1+

A2+

A2+

B1+

B1+

B2+

B2+

C

TDI

TMS

INSELC

INSELB

V

CC

ULCD

ULCC

GND

DATA

DATA

DATA

DATA

GND

V

SPD

V

LDTD

TRST

GND

TDO

[7]

[5]

[3]

[1]

CC

SELD

CC

EN

D

TCLK

RESET

INSELD

INSELA

V

CC

ULCA

SPD

GND

DATA

DATA

DATA

DATA

GND

GND

ULCB

V

NC

V

SCAN

TMEN3

SELC

[6]

[4]

[2]

[0]

CC

CC

EN2

E

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

F

RX

RX

VCC

VCC

VCC

RX

RE

RX

DC[8]

DC[9]

DB[0]

CLKOB

DB[1]

G

GND

WREN

GND

GND

SPD

NC

SPD

RX

SELB

SELA

DB[3]

H

GND

GND

GND

GND

GND

GND

GND

GND

J

GND

GND

GND

GND

BIST

RX

RX

RX

STB

DB[2]

DB[7]

DB[4]

K

RX

TRG

GND

GND

RX

RX

RX

LFIB

DC[4]

CLKC–

DB[5]

DB[6]

DB[9]

L

RX

TRG

LFIC

GND

RX

RX

RX

GND

DC[5]

CLKC+

DB[8]

CLKB+

CLKB–

M

RX

RX

VCC

RE

TRG

TRG

RE

GND

DC[6]

DC[7]

PDOC

CLKB+

CLKB–

PDOB

N

GND

GND

GND

GND

GND

GND

GND

GND

P

RX

RX

RX

RX

GND

GND

GND

GND

DC[3]

DC[2]

DC[1]

DC[0]

R

BIST

RE

RX

RX

VCC

VCC

VCC

VCC

STC

CLKOC

CLKC+

CLKC–

T

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

U

VCC

VCC

VCC

VCC

VCC

RX

RX

GND

GND

ADDR

TRG

GND

GND

GND

VCC

VCC

RX

VCC

BIST

RX

DD[4]

DD[3]

[0]

CLKD–

DA[4]

STA

DA[0]

V

VCC

VCC

VCC

RX

VCC

RX

RX

GND

BIST

ADDR

TRG

RE

GND

GND

VCC

VCC

RX

RX

RX

RX

DD[8]

DD[5]

DD[1]

STD

[2]

CLKD+

CLKOA

DA[9]

DA[5]

DA[2]

DA[1]

W

VCC

VCC

LFID

RX

VCC

RX

RX

GND

ADDR

ADDR

RX

RE

GND

GND

VCC

VCC

LFIA

TRG

RX

RX

CLKD–

DD[6]

DD[0]

[3]

[1]

CLKA+

PDOA

CLKA+

DA[6]

DA[3]

Y

VCC

VCC

RX

RX

VCC

RX

RX

GND

RE

NC

GND

RX

GND

GND

VCC

VCC

RE

TRG

RX

RX

DD[9]

CLKD+

DD[7]

DD[2]

CLKOD

CLKA–

PDOD

CLKA–

DA[8]

DA[7]

Note

1. NC = Do not connect.

Document #: 38-02102 Rev. *C

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Contents Features Functional DescriptionCypress Semiconductor Corporation CYV15G0404RB Deserializing Reclocker Logic Block Diagram Reclocking Deserializer Path Block Diagram Clock Device Configuration and Control Block Diagram = Internal SignalPin Configuration Top View1 Pin Configuration Bottom View1 Receive Path Clock Signals Device Control SignalsAsynchronous Device Reset Device Configuration and Control Bus Signals Name IO Characteristics Signal DescriptionLink Fault Indication Output Control Write Enable .Receive Channel Power Control Internal Device Configuration LatchesSignal Detect Amplitude Select Receive Bist DisabledCYV15G0404RB HOTLink II Operation CYV15G0404RB Receive Data PathHigh Clock/Data RecoveryLOW ReclockerPower Control Device Configuration and Control InterfaceLatch Types Force Global Enable FunctionMask Function Static Latch ValuesDevice Configuration Strategy Device Control Latch Configuration Table DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0Jtag Support Receive Bist Status BitsLevel Select Inputs Bistwait RX PLLBiststart Bistdatacompare 000CYV15G0404RB DC Electrical Characteristics Operating Range Maximum RatingsCYV15G0404RB DC Electrical Characteristics AC Test Loads and WaveformsCYV15G0404RB AC Electrical Characteristics Parameter Description Min Max Unit CYV15G0404RB Device PLL CharacteristicsCapacitance14 Parameter Description Test Conditions Max UnitBus Configuration Write Timing Receive Interface Read Timing RXRATEx =Lvttl in PU VCC PowerCML CML OUTRXDB8 Lvttl OUT ROUTB2+ CML OUTTDI Lvttl in PU TMS Lvttl in PUSpeed Ordering Code Package Package Type Operating Package DiagramOrdering Information RangeSUA Document HistoryFRE AGT