Cypress manual Maximum Ratings, CYV15G0404RB DC Electrical Characteristics Operating Range

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CYV15G0404RB

Maximum Ratings

Excedding maximum ratings may shorten the device life. User guidelines are not tested

Storage Temperature

–65°C to +150°C

Ambient Temperature with

 

Power Applied

–55°C to +125°C

Supply Voltage to Ground Potential

–0.5V to +3.8V

Static Discharge Voltage

> 2000 V

(MIL-STD-883, Method 3015)

 

Latch Up Current

> 200 mA

Power Up Requirements

The CYV15G0404RB requires one power supply. The voltage on any input or I/O pin cannot exceed the power pin during power up.

DC Voltage Applied to LVTTL Outputs

 

 

in High-Z State

–0.5V to VCC + 0.5V

Output Current into LVTTL Outputs (LOW)

60 mA

DC Input Voltage

–0.5V to VCC + 0.5V

CYV15G0404RB DC Electrical Characteristics

Operating Range

Range

Ambient Temperature

VCC

Commercial

0°C to +70°C

+3.3V ±5%

 

 

 

Parameter

Description

Test Conditions

Min

Max

Unit

 

 

 

 

 

 

LVTTL-compatible Outputs

 

 

 

 

 

 

 

 

 

 

VOHT

Output HIGH Voltage

IOH = 4 mA, VCC = Min.

2.4

 

V

VOLT

Output LOW Voltage

IOL = 4 mA, VCC = Min.

 

0.4

V

IOST

Output Short Circuit Current

VOUT = 0V[6], VCC = 3.3V

–20

–100

mA

IOZL

High-Z Output Leakage Current

VOUT = 0V, VCC

–20

20

µA

LVTTL-compatible Inputs

 

 

 

 

 

 

 

 

 

 

VIHT

Input HIGH Voltage

 

2.0

VCC + 0.3

V

VILT

Input LOW Voltage

 

–0.5

0.8

V

IIHT

Input HIGH Current

TRGCLKx Input, VIN = VCC

 

1.5

mA

 

 

Other Inputs, VIN = VCC

 

+40

µA

IILT

Input LOW Current

TRGCLKx Input, VIN = 0.0V

 

–1.5

mA

 

 

Other Inputs, VIN = 0.0V

 

–40

µA

IIHPDT

Input HIGH Current with Internal Pull Down

VIN = VCC

 

+200

µA

IILPUT

Input LOW Current with Internal Pull Up

VIN = 0.0V

 

–200

µA

LVDIFF Inputs: TRGCLKx±

 

 

 

 

 

 

 

 

 

 

VDIFF[7]

Input Differential Voltage

 

400

VCC

mV

VIHHP

Highest Input HIGH Voltage

 

1.2

VCC

V

VILLP

Lowest Input LOW voltage

 

0.0

VCC/2

V

VCOMREF[8]

Common Mode Range

 

1.0

VCC – 1.2V

V

3-Level Inputs

 

 

 

 

 

 

 

 

 

 

VIHH

Three-Level Input HIGH Voltage

Min. VCC Max.

0.87 * VCC

VCC

V

VIMM

Three-Level Input MID Voltage

Min. VCC Max.

0.47 * VCC

0.53 * VCC

V

VILL

Three-Level Input LOW Voltage

Min. VCC Max.

0.0

0.13 * VCC

V

IIHH

Input HIGH Current

VIN = VCC

 

200

µA

IIMM

Input MID current

VIN = VCC/2

–50

50

µA

IILL

Input LOW current

VIN = GND

 

–200

µA

Notes

6.Tested one output at a time, output shorted for less than one second, less than 10% duty cycle.

7.This is the minimum difference in voltage between the true and complement inputs required to ensure detection of a logic-1 or logic-0. A logic-1 exists when the true (+) input is more positive than the complement () input. A logic-0 exists when the complement () input is more positive than true (+) input.

8.The common mode range defines the allowable range of TRGCLKx+ and TRGCLKxwhen TRGCLKx+ = TRGCLKx. This marks the zero-crossing between the true and complement inputs as the signal switches between a logic-1 and a logic-0.

Document #: 38-02102 Rev. *C

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Contents Functional Description FeaturesCypress Semiconductor Corporation CYV15G0404RB Deserializing Reclocker Logic Block Diagram Reclocking Deserializer Path Block Diagram Clock = Internal Signal Device Configuration and Control Block DiagramPin Configuration Top View1 Pin Configuration Bottom View1 Device Control Signals Receive Path Clock SignalsAsynchronous Device Reset Control Write Enable . Name IO Characteristics Signal DescriptionLink Fault Indication Output Device Configuration and Control Bus SignalsReceive Bist Disabled Internal Device Configuration LatchesSignal Detect Amplitude Select Receive Channel Power ControlCYV15G0404RB Receive Data Path CYV15G0404RB HOTLink II OperationReclocker Clock/Data RecoveryLOW HighDevice Configuration and Control Interface Power ControlStatic Latch Values Force Global Enable FunctionMask Function Latch TypesDevice Configuration Strategy DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Device Control Latch Configuration TableReceive Bist Status Bits Jtag SupportLevel Select Inputs Bistdatacompare 000 RX PLLBiststart BistwaitMaximum Ratings CYV15G0404RB DC Electrical Characteristics Operating RangeAC Test Loads and Waveforms CYV15G0404RB DC Electrical CharacteristicsCYV15G0404RB AC Electrical Characteristics Parameter Description Test Conditions Max Unit PLL CharacteristicsCapacitance14 Parameter Description Min Max Unit CYV15G0404RB DeviceReceive Interface Read Timing RXRATEx = Bus Configuration Write TimingCML OUT VCC PowerCML Lvttl in PUTMS Lvttl in PU ROUTB2+ CML OUTTDI Lvttl in PU RXDB8 Lvttl OUTRange Package DiagramOrdering Information Speed Ordering Code Package Package Type OperatingAGT Document HistoryFRE SUA