Cypress CYV15G0404RB manual Jtag Support, Receive Bist Status Bits, Level Select Inputs

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CYV15G0404RB

JTAG Support

The CYV15G0404RB contains a JTAG port to allow system level diagnosis of device interconnect. Of the available JTAG modes, boundary scan and bypass are supported. This capability is present only on the LVTTL inputs and outputs and the TRGCLKx± clock input. The high-speed serial inputs and outputs are not part of the JTAG test chain.

To ensure valid device operation after power-up (including non-JTAG operation), the JTAG state machine must also be initialized to a reset state. This must be done in addition to the device reset (using RESET). Initialize the JTAG state machine using TRST (assert it LOW and deassert it or leave it asserted), or by asserting TMS HIGH for at least 5 consecutive TCLK cycles. This is necessary in order to ensure that the

Table 5. Receive BIST Status Bits

JTAG controller does not enter any of the test modes after device power-up. In this JTAG reset state, the rest of the device will operate normally.

Note The order of device reset (using RESET) and JTAG initialization does not matter.

3-Level Select Inputs

Each 3-Level select input reports as two bits in the scan register. These bits report the LOW, MID, and HIGH state of the associated input as 00, 10, and 11 respectively

JTAG ID

The JTAG device ID for the CYV15G0404RB is ‘0C811069’x.

{BISTSTx, RXDx[0],

Description

Receive BIST Status

RXDx[1]}

 

(Receive BIST = Enabled)

000, 001

BIST Data Compare. Character compared correctly.

010

BIST Last Good. Last Character of BIST sequence detected and valid.

 

 

011

Reserved.

 

 

100

BIST Last Bad. Last Character of BIST sequence detected invalid.

101

BIST Start. Receive BIST is enabled on this channel, but character compares have not yet

 

commenced. This also indicates a PLL Out of Lock condition.

110

BIST Error. While comparing characters, a mismatch was found in one or more of the character bits.

 

 

111

BIST Wait. The receiver is comparing characters, but has not yet found the start of BIST character to

 

enable the LFSR.

Document #: 38-02102 Rev. *C

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Contents Cypress Semiconductor Corporation FeaturesFunctional Description CYV15G0404RB Deserializing Reclocker Logic Block Diagram Reclocking Deserializer Path Block Diagram Clock = Internal Signal Device Configuration and Control Block DiagramPin Configuration Top View1 Pin Configuration Bottom View1 Asynchronous Device Reset Receive Path Clock SignalsDevice Control Signals Link Fault Indication Output Name IO Characteristics Signal DescriptionDevice Configuration and Control Bus Signals Control Write Enable .Signal Detect Amplitude Select Internal Device Configuration LatchesReceive Channel Power Control Receive Bist DisabledCYV15G0404RB Receive Data Path CYV15G0404RB HOTLink II OperationLOW Clock/Data RecoveryHigh ReclockerDevice Configuration and Control Interface Power ControlMask Function Force Global Enable FunctionLatch Types Static Latch ValuesDevice Configuration Strategy DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Device Control Latch Configuration TableLevel Select Inputs Jtag SupportReceive Bist Status Bits Biststart RX PLLBistwait Bistdatacompare 000Maximum Ratings CYV15G0404RB DC Electrical Characteristics Operating RangeAC Test Loads and Waveforms CYV15G0404RB DC Electrical CharacteristicsCYV15G0404RB AC Electrical Characteristics Capacitance14 PLL CharacteristicsParameter Description Min Max Unit CYV15G0404RB Device Parameter Description Test Conditions Max UnitReceive Interface Read Timing RXRATEx = Bus Configuration Write TimingCML VCC PowerLvttl in PU CML OUTTDI Lvttl in PU ROUTB2+ CML OUTRXDB8 Lvttl OUT TMS Lvttl in PUOrdering Information Package DiagramSpeed Ordering Code Package Package Type Operating RangeFRE Document HistorySUA AGT