Cypress CYV15G0404RB manual Document History, Fre, Sua, Agt, Kkvtmp

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CYV15G0404RB

Document History Page

Document Title: CYV15G0404RB Independent Clock Quad HOTLink II™ Deserializing Reclocker

Document Number: 38-02102

REV.	ECN NO.	ISSUE	ORIG. OF	DESCRIPTION OF CHANGE
REV.	ECN NO.	DATE	CHANGE	DESCRIPTION OF CHANGE
		DATE	CHANGE

**	246850	See ECN	FRE	New Data Sheet

*A	338721	See ECN	SUA	Added Pb-Free package option availability

*B	384307	See ECN	AGT	Revised setup and hold times (tRXDv–, tRXDv+)
*C	789283	See ECN	KKVTMP	Clarification to the need and procedure to initialize the JTAG controller
				(during test and non-test mode) to ensure valid device power-up. No
				changes have been made to the device specifications or character-
				estics.

Document #: 38-02102 Rev. *C

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Contents Features Functional DescriptionCypress Semiconductor Corporation CYV15G0404RB Deserializing Reclocker Logic Block Diagram Reclocking Deserializer Path Block Diagram Clock = Internal Signal Device Configuration and Control Block DiagramPin Configuration Top View1 Pin Configuration Bottom View1 Receive Path Clock Signals Device Control SignalsAsynchronous Device Reset Control Write Enable . Name IO Characteristics Signal DescriptionLink Fault Indication Output Device Configuration and Control Bus SignalsReceive Bist Disabled Internal Device Configuration LatchesSignal Detect Amplitude Select Receive Channel Power ControlCYV15G0404RB Receive Data Path CYV15G0404RB HOTLink II OperationReclocker Clock/Data RecoveryLOW HighDevice Configuration and Control Interface Power ControlStatic Latch Values Force Global Enable FunctionMask Function Latch TypesDevice Configuration Strategy DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Device Control Latch Configuration TableJtag Support Receive Bist Status BitsLevel Select Inputs Bistdatacompare 000 RX PLLBiststart BistwaitMaximum Ratings CYV15G0404RB DC Electrical Characteristics Operating RangeAC Test Loads and Waveforms CYV15G0404RB DC Electrical CharacteristicsCYV15G0404RB AC Electrical Characteristics Parameter Description Test Conditions Max Unit PLL CharacteristicsCapacitance14 Parameter Description Min Max Unit CYV15G0404RB DeviceReceive Interface Read Timing RXRATEx = Bus Configuration Write TimingCML OUT VCC PowerCML Lvttl in PUTMS Lvttl in PU ROUTB2+ CML OUTTDI Lvttl in PU RXDB8 Lvttl OUTRange Package DiagramOrdering Information Speed Ordering Code Package Package Type OperatingAGT Document HistoryFRE SUA

Document History Page

REV.

ECN NO.

ISSUE

ORIG. OF

DESCRIPTION OF CHANGE

DATE

FRE

SUA

AGT

KKVTMP