Cypress CYV15G0404RB manual Pin Configuration Bottom View1

Page 7

CYV15G0404RB

Pin Configuration (Bottom View)[1]

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

A

ROUT

IN

ROUT

IN

VCC

ROUT

IN

GND

ROUT

IN

ROUT

IN

GND

ROUT

IN

VCC

ROUT

IN

ROUT

IN

B2–

B2–

B1–

B1–

A2–

A2–

A1–

A1–

D2–

D2–

D1–

D1–

C2–

C2–

C1–

C1–

B

ROUT

IN

ROUT

IN

VCC

ROUT

IN

GND

ROUT

IN

ROUT

IN

GND

ROUT

IN

VCC

ROUT

IN

ROUT

IN

B2+

B2+

B1+

B1+

A2+

A2+

A1+

A1+

D2+

D2+

D1+

D1+

C2+

C2+

C1+

C1+

TDO

GND

LDTD

VCC

SPD

VCC

GND

DATA

DATA

DATA

DATA

GND

VCC

INSELB

INSELC

TMS

TDI

C

TRST

ULCC

ULCD

EN

SELD

[1]

[3]

[5]

[7]

TMEN3

SCAN

DATA

DATA

DATA

DATA

SPD

INSELA

INSELD

TCLK

D

VCC

NC

VCC

ULCB

GND

GND

GND

ULCA

VCC

RESET

EN2

[0]

[2]

[4]

[6]

SELC

E

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

F

RX

RE

RX

VCC

VCC

VCC

RX

RX

DB[1]

CLKOB

DB[0]

DC[9]

DC[8]

RX

SPD

NC

SPD

GND

GND

GND

G

WREN

DB[3]

SELA

SELB

H

GND

GND

GND

GND

GND

GND

GND

GND

J

RX

RX

RX

BIST

GND

GND

GND

GND

DB[4]

DB[7]

DB[2]

STB

RX

RX

RX

TRG

RX

K

LFIB

GND

GND

DB[9]

DB[6]

DB[5]

CLKC–

DC[4]

RX

RX

RX

TRG

RX

L

GND

GND

LFIC

CLKB–

CLKB+

DB[8]

CLKC+

DC[5]

M

GND

RE

TRG

TRG

RE

VCC

RX

RX

PDOB

CLKB–

CLKB+

PDOC

DC[7]

DC[6]

N

GND

GND

GND

GND

GND

GND

GND

GND

P

GND

GND

GND

GND

RX

RX

RX

RX

DC[0]

DC[1]

DC[2]

DC[3]

R

VCC

VCC

VCC

VCC

RX

RX

RE

BIST

CLKC–

CLKC+

CLKOC

STC

T

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

U

RX

BIST

VCC

RX

VCC

VCC

GND

GND

GND

TRG

ADDR

GND

GND

RX

RX

VCC

VCC

VCC

VCC

VCC

DA[0]

STA

DA[4]

CLKD–

[0]

DD[3]

DD[4]

V

RX

RX

RX

RX

VCC

VCC

GND

GND

RE

TRG

ADDR

BIST

GND

RX

RX

VCC

RX

VCC

VCC

VCC

DA[1]

DA[2]

DA[5]

DA[9]

CLKOA

CLKD+

[2]

STD

DD[1]

DD[5]

DD[8]

RX

RX

TRG

RE

RX

ADDR

ADDR

RX

RX

RX

W

LFIA

VCC

VCC

GND

GND

GND

VCC

LFID

VCC

VCC

DA[3]

DA[6]

CLKA+

PDOA

CLKA+

[1]

[3]

DD[0]

DD[6]

CLKD–

Y

RX

RX

TRG

RE

VCC

VCC

GND

GND

RX

GND

NC

RE

GND

RX

RX

VCC

RX

RX

VCC

VCC

DA[7]

DA[8]

CLKA–

PDOD

CLKA–

CLKOD

DD[2]

DD[7]

CLKD+

DD[9]

Document #: 38-02102 Rev. *C

Page 7 of 27

[+] Feedback

Image 7

Contents Functional Description FeaturesCypress Semiconductor Corporation CYV15G0404RB Deserializing Reclocker Logic Block Diagram Reclocking Deserializer Path Block Diagram Clock = Internal Signal Device Configuration and Control Block DiagramPin Configuration Top View1 Pin Configuration Bottom View1 Device Control Signals Receive Path Clock SignalsAsynchronous Device Reset Control Write Enable . Name IO Characteristics Signal DescriptionLink Fault Indication Output Device Configuration and Control Bus SignalsReceive Bist Disabled Internal Device Configuration LatchesSignal Detect Amplitude Select Receive Channel Power ControlCYV15G0404RB Receive Data Path CYV15G0404RB HOTLink II OperationReclocker Clock/Data RecoveryLOW HighDevice Configuration and Control Interface Power ControlStatic Latch Values Force Global Enable FunctionMask Function Latch TypesDevice Configuration Strategy DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Device Control Latch Configuration TableReceive Bist Status Bits Jtag SupportLevel Select Inputs Bistdatacompare 000 RX PLLBiststart BistwaitMaximum Ratings CYV15G0404RB DC Electrical Characteristics Operating RangeAC Test Loads and Waveforms CYV15G0404RB DC Electrical CharacteristicsCYV15G0404RB AC Electrical Characteristics Parameter Description Test Conditions Max Unit PLL CharacteristicsCapacitance14 Parameter Description Min Max Unit CYV15G0404RB DeviceReceive Interface Read Timing RXRATEx = Bus Configuration Write TimingCML OUT VCC PowerCML Lvttl in PUTMS Lvttl in PU ROUTB2+ CML OUTTDI Lvttl in PU RXDB8 Lvttl OUTRange Package DiagramOrdering Information Speed Ordering Code Package Package Type OperatingAGT Document HistoryFRE SUA