Cypress CYV15G0404RB manual Ordering Information, Package Diagram, Range

Page 26

CYV15G0404RB

Table 6. Package Coordinate Signal Allocation (continued)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ball

Signal Name

Signal Type

 

Ball

Signal Name

Signal Type

 

Ball

Signal Name

Signal Type

ID

 

 

 

ID

 

 

 

ID

 

 

T03

VCC

POWER

 

V15

VCC

POWER

 

Y15

VCC

POWER

 

 

 

 

 

 

 

 

 

 

 

T04

VCC

POWER

 

V16

VCC

POWER

 

Y16

VCC

POWER

 

 

 

 

 

 

 

 

 

 

 

T17

VCC

POWER

 

V17

RXDA[9]

LVTTL OUT

 

Y17

REPDOD

LVTTL OUT

 

 

 

 

 

 

 

 

 

 

 

T18

VCC

POWER

 

V18

RXDA[5]

LVTTL OUT

 

Y18

TRGCLKA–

PECL IN

 

 

 

 

 

 

 

 

 

 

 

T19

VCC

POWER

 

V19

RXDA[2]

LVTTL OUT

 

Y19

RXDA[8]

LVTTL OUT

 

 

 

 

 

 

 

 

 

 

 

T20

VCC

POWER

 

V20

RXDA[1]

LVTTL OUT

 

Y20

RXDA[7]

LVTTL OUT

 

 

 

 

 

 

 

 

 

 

 

U01

VCC

POWER

 

W01

VCC

POWER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

U02

VCC

POWER

 

W02

VCC

POWER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ordering Information

Speed

Ordering Code

Package

Package Type

Operating

Name

Range

 

 

 

 

 

 

 

 

Standard

CYV15G0404RB-BGC

BL256

256-Ball Thermally Enhanced Ball Grid Array

Commercial

 

 

 

 

 

Standard

CYV15G0404RB-BGXC

BL256

Pb-Free 256-Ball Thermally Enhanced Ball Grid Array

Commercial

 

 

 

 

 

Package Diagram

Figure 3. 256-Lead L2 Ball Grid Array (27 x 27 x 1.57 mm) BL256

TOP VIEW

27.00±0.13

A1 CORNER I.D.

0.20(4X)

 

 

BOTTOM VIEW (BALL SIDE)

 

A

 

Ø0.15 M C

 

 

 

 

 

 

 

 

 

 

 

 

Ø0.30 M C

A

B

 

 

 

 

24.13

 

 

 

 

Ø0.75±0.15(256X)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

20

18

 

16

14

12

10

8

6

4

2

 

 

 

19

17

15

13

11

9

7

5

3

1

 

 

 

 

 

 

 

 

 

 

 

 

A

 

 

 

 

 

 

 

 

 

 

 

 

B

 

 

 

 

 

 

 

 

 

 

 

 

C

 

 

 

 

 

 

 

 

 

 

 

 

D

 

 

 

 

 

 

 

 

 

 

 

 

E

 

 

 

 

 

 

 

 

 

 

 

 

F

 

 

 

 

 

 

 

 

 

 

 

 

G

 

 

 

 

 

 

 

R 2.5 Max (4X)

 

 

H

27.00±0.13

 

 

 

 

 

 

 

 

 

 

 

J

 

 

 

 

 

 

 

 

 

 

 

K

 

 

 

 

 

 

 

 

 

 

 

L

 

 

 

 

 

 

 

 

 

 

 

M

 

 

 

 

 

 

 

 

 

 

 

N

 

A

 

 

 

 

 

 

 

 

 

P

 

 

 

 

 

 

 

 

 

 

 

R

T

U

V

W

Y

A1 CORNER I.D.

12.065

24.13

1.27

1.57±0.175

0.97 REF.

0.60±0.10

C

 

B

 

 

0.15

C

26°

0.15

C

 

TYP.

 

 

SEATING PLANE

0.50 MIN.

A

0.20 MIN

TOP OF MOLD COMPOUND TO TOP OF BALLS

SIDE VIEW

51-85123-*E

 

SECTION A-A

HOTLink is a registered trademark and HOTLink II is a trademark of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders.

Document #: 38-02102 Rev. *C

Page 26 of 27

© Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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Contents Cypress Semiconductor Corporation FeaturesFunctional Description CYV15G0404RB Deserializing Reclocker Logic Block Diagram Reclocking Deserializer Path Block Diagram Clock Device Configuration and Control Block Diagram = Internal SignalPin Configuration Top View1 Pin Configuration Bottom View1 Asynchronous Device Reset Receive Path Clock SignalsDevice Control Signals Device Configuration and Control Bus Signals Name IO Characteristics Signal DescriptionLink Fault Indication Output Control Write Enable .Receive Channel Power Control Internal Device Configuration LatchesSignal Detect Amplitude Select Receive Bist DisabledCYV15G0404RB HOTLink II Operation CYV15G0404RB Receive Data PathHigh Clock/Data RecoveryLOW ReclockerPower Control Device Configuration and Control InterfaceLatch Types Force Global Enable FunctionMask Function Static Latch ValuesDevice Configuration Strategy Device Control Latch Configuration Table DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0Level Select Inputs Jtag SupportReceive Bist Status Bits Bistwait RX PLLBiststart Bistdatacompare 000CYV15G0404RB DC Electrical Characteristics Operating Range Maximum RatingsCYV15G0404RB DC Electrical Characteristics AC Test Loads and WaveformsCYV15G0404RB AC Electrical Characteristics Parameter Description Min Max Unit CYV15G0404RB Device PLL CharacteristicsCapacitance14 Parameter Description Test Conditions Max UnitBus Configuration Write Timing Receive Interface Read Timing RXRATEx =Lvttl in PU VCC PowerCML CML OUTRXDB8 Lvttl OUT ROUTB2+ CML OUTTDI Lvttl in PU TMS Lvttl in PUSpeed Ordering Code Package Package Type Operating Package DiagramOrdering Information RangeSUA Document HistoryFRE AGT